search for: exedomain

...; } class Domain<bits<2> val> { bits<2> Value = val; } def GenericDomain : Domain<0>; def SSEPackedInt : Domain<1>; def SSEPackedSingle : Domain<2>; def SSEPackedDouble : Domain<3>; class X86Instr<bits<8> opcod> : Instruction { Domain ExeDomain = GenericDomain; let TSFlags{0-7} = opcod; let TSFlags{22-23} = ExeDomain.Value; } class PIInstr<bits<8> opcod> : X86Instr<opcod> { let ExeDomain = SSEPackedInt; } def i1 : X86Instr<0x12>; def i2 : PIInstr<0x34>; def i3 : PIInstr<0x34> { let ExeDomain = S...

Hi, I noticed, that execution domain is set to SSEPackedSingle for these instructions. Looks like a bug. let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in { def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst), - Elena --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended...

...128rr, X86::VPERM2I128rr } On Wed, Jan 4, 2012 at 4:32 AM, Demikhovsky, Elena < elena.demikhovsky at intel.com> wrote: > Hi, > > I noticed, that execution domain is set to SSEPackedSingle for these > instructions. > Looks like a bug. > > let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in { > def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst), > > - Elena > > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential m...

...X86::VPERM2I128rr } On Wed, Jan 4, 2012 at 4:32 AM, Demikhovsky, Elena <elena.demikhovsky at intel.com<mailto:elena.demikhovsky at intel.com>> wrote: Hi, I noticed, that execution domain is set to SSEPackedSingle for these instructions. Looks like a bug. let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in { def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst), - Elena --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended...

...mask_wb in the pattern below. > > multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, > X86MemOperand memop, PatFrag GatherNode> { > let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb", > ExeDomain = _.ExeDomain in > def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb), > (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2), > !strconcat(OpcodeStr#_.Suffix, > "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), >...

Hal, that’s a good point. There are more manually-maintained tables in the X86 backend that should probably be tablegened: the memory-folding tables and ReplaceableInstrs, to name a couple. If you have ideas on how to get these auto-generated, please let us know. From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Hal Finkel via llvm-dev Sent: Wednesday, November 23, 2016

...ing OpcodeStr, >>>>> X86VectorVTInfo _, >>>>> X86MemOperand memop, PatFrag GatherNode> { >>>>> let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = >>>>> $mask_wb", >>>>> ExeDomain = _.ExeDomain in >>>>> def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, >>>>> _.KRCWM:$mask_wb), >>>>> (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2), >>>>> !strconcat(OpcodeStr#_.Suffix, >>>>>...

i want to implement gather for v64i32. i wrote following code. def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins i2048mem:$src), "GATHER_256B\t{$src, $dst|$dst, $src}", [(set VR_2048:$dst, (v64i32 (masked_gather addr:$src)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B