search for: evex_4v

I was getting same error when i keep both EVEX/EVEX_4V and TA. So, i restored my original instructions and for that i have to include bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; in order to emit binary correctly. Is it right? On Tue, Sep 5, 2017 at 5:45 AM, Craig Topper &lt...

Thank You, I changed TA to EVEX or EVEX_4V. But now i am getting following error: Invalid prefix! UNREACHABLE executed at /lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp:647! On Tue, Sep 5, 2017 at 4:36 AM, Craig Topper <craig.topper at gmail.com> wrote: > Not all instructions can use EVEX_4V. Move instructions in particular...

Thank You. I used EVEX_4V with all the instructions. I replaced TA and EVEX both with EVEX_4V. Now, I am getting following error: llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void llvm::X86Disassembler::RecognizableInstr::emitInstructionSpecifier(): Assertion `numPhysicalOperands >= 2 + additionalOperands...

...gt;>>> >>>> Is it right way? >>>> >>>> >>>> >>>> On Tue, Sep 5, 2017 at 3:29 AM, Craig Topper <craig.topper at gmail.com> >>>> wrote: >>>> >>>>> Does your ADD instruction have VEX_4V or EVEX_4V as part of its >>>>> declaration in the td file? >>>>> >>>>> ~Craig >>>>> >>>>> On Mon, Sep 4, 2017 at 2:11 PM, hameeza ahmed <hahmed2305 at gmail.com> >>>>> wrote: >>>>> >>>>&...

...So far i made no changes or additions in MC framework or any of the file (except the above discussed) and still getting the correct machine code. Is it right way? On Tue, Sep 5, 2017 at 3:29 AM, Craig Topper <craig.topper at gmail.com> wrote: > Does your ADD instruction have VEX_4V or EVEX_4V as part of its > declaration in the td file? > > ~Craig > > On Mon, Sep 4, 2017 at 2:11 PM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> Hello, >> I am trying to emit binary for my implemented vector instructions. >> Although yet i havent done a...

...above discussed) and still getting the >> correct machine code. >> >> Is it right way? >> >> >> >> On Tue, Sep 5, 2017 at 3:29 AM, Craig Topper <craig.topper at gmail.com> >> wrote: >> >>> Does your ADD instruction have VEX_4V or EVEX_4V as part of its >>> declaration in the td file? >>> >>> ~Craig >>> >>> On Mon, Sep 4, 2017 at 2:11 PM, hameeza ahmed <hahmed2305 at gmail.com> >>> wrote: >>> >>>> Hello, >>>> I am trying to emit binary for m...

Hello, I am trying to emit binary for my implemented vector instructions. Although yet i havent done any change or addition in MC framework, For vector load instruction there are no error coming. But for vector add instruction is something like this; > %R_0_REG2048b_1<def> = P_256B_VADD %R_0_REG2048b_1<kill>, %R_0_REG2048b_0<kill> I am getting the following error: Unknown

...map to TA and prefix to XD VEX - Set encoding to VEX. VEX_W - Set VEX_WPrefix to VEX.W=1 VEX_WIG - VEX_WPrefix to VEX.W ignore value. VEX_4V - Set hasVEX_4V=1. Implies VEX. VEX_L - set hasVEX_L=1 VEX_LIG - Set ignoresVEX_L EVEX - Set encoding to EVEX. EVEX_4V - Set hasVEX_4V=1. Implies EVEX. EVEX_K - Set hasEVEX_K=1. EVEX_KZ - Set hasEVEX_Z=1. Implies EVEX_K. EVEX_B - Set hasEVEX_B=1 EVEX_RC - Set hasEVEX_RC=1 EVEX_V512 - Sets has_EVEX_L2=1; hasVEX_L=0; EVEX_V256 - Sets has_EVEX_L2=0; hasVEX_L=1; EVEX_V128 - Sets has_...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

Thank You. Still getting errors.I have modified my instructions as you said as follows: def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst, VK64WM:$mask_wb), (ins VR_2048:$src1, VK64WM:$mask, i2048mem:$src2), "GATHER_256B\t{$src2, {$dst} {${mask}}|${dst} {${mask}}, $src2}", [(set VR_2048:$dst, VK64WM:$mask_wb, (v64i32 (masked_gather