Displaying 3 results from an estimated 3 matches for "estruct".
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2017 Mar 11
3
Is there a way to know the target's L1 data cache line size?
I guess that in this case, what I would like to know is a reasonable
upper bound of the cache line size on the target architecture. Something
that I can align my data structures on at compile time so as to minimize
the odds of false sharing. Think
std::hardware_destructive_interference_size in C++17.
Le 11/03/2017 à 13:16, Bruce Hoult a écrit :
> There's no way to know, until you run on real hardware. It could be
> different every time the binary is run. You have to ask the OS or
> hardware, and that's system dependent.
>
> The cache line...
2017 Mar 11
2
Is there a way to know the target's L1 data cache line size?
Hi everyone,
I'm hailing from the Rust community, where there is a discussion about
adding facilities for aligning data on an L1 cache line boundary. One
example of situation where this is useful is when building thread
synchronization primitives, where avoiding false sharing can be a
critical concern.
Now, when it comes to implementation, I have this gut feeling that we
probably do not
2017 Mar 11
2
Is there a way to know the target's L1 data cache line size?
...I guess that in this case, what I would like to know is a
> reasonable upper bound of the cache line size on the target
> architecture. Something that I can align my data structures on at
> compile time so as to minimize the odds of false sharing. Think
> std::hardware_destructive_interference_size in C++17.
>
>
> Le 11/03/2017 à 13:16, Bruce Hoult a écrit :
>> There's no way to know, until you run on real hardware. It could
>> be different every time the binary is run. You have to ask the OS
>> or hardware, and that's sy...