Displaying 9 results from an estimated 9 matches for "esenciaisd".
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
...tFlag and another in SF_RI class
(specifically in its DAG pattern).
Any help is appreciated.
========================= Orignal Code =====================================
def SDT_EsenciaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
def Esencia_CC_LT : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETLT);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (in...
2016 Mar 15
4
view how instruction selection is happening
...how instruction
selection is happening. The output I'm talking about is shown below. Can
someone remind me how to generate it? (I really should start writing down
stuff like this)
========================= Orignal Match Result
=====================================
Selecting: 0x2ebfa78: glue = EsenciaISD::SET_FLAG 0x2ebee18, 0x2ebef20,
0x2ebf658 [ORD=3] [ID=11]
ISEL: Starting pattern match on root node: 0x2ebfa78: glue =
EsenciaISD::SET_FLAG 0x2ebee18, 0x2ebef20, 0x2ebf658 [ORD=3] [ID=11]
Initial Opcode index to 258
Skipped scope entry (due to false predicate) at index 278, continuing at
292...
2016 Feb 18
4
How to interpret Selection DAG error output
...terns for my target. Conceptually I
understand what DAG patterns are and what is their purpose, however given
that I have quite vague understanding about how to LLVM implements and
specifies them, naturally I got an error. Here it is
Here is the error:
LLVM ERROR: Cannot select: 0x3284268: glue = EsenciaISD::SET_FLAG
0x3283608, 0x3283710, 0x3283e48 [ORD=3] [ID=11]
0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] [ID=9]
0x3283500: i32 = Register %vreg5 [ID=1]
0x3283710: i32 = Constant<3> [ID=2]
0x3283e48: i32 = Constant<20> [ID=8]
In function: fib
As far as I can unde...
2016 Feb 18
3
How to interpret Selection DAG error output
On Thu, Feb 18, 2016 at 10:50 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 2/18/2016 12:43 PM, Rail Shafigulin via llvm-dev wrote:
>
>>
>> LLVM ERROR: Cannot select: 0x3284268: glue = EsenciaISD::SET_FLAG
>> 0x3283608, 0x3283710, 0x3283e48 [ORD=3] [ID=11]
>> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] [ID=9]
>> 0x3283500: i32 = Register %vreg5 [ID=1]
>> 0x3283710: i32 = Constant<3> [ID=2]
>> 0x3283e48: i32 = Constant<20&...
2016 Feb 18
3
How to interpret Selection DAG error output
...at 10:50 AM, Krzysztof Parzyszek via llvm-dev
>> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>
>> On 2/18/2016 12:43 PM, Rail Shafigulin via llvm-dev wrote:
>>
>>
>> LLVM ERROR: Cannot select: 0x3284268: glue = EsenciaISD::SET_FLAG
>> 0x3283608, 0x3283710, 0x3283e48 [ORD=3] [ID=11]
>> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1]
>> [ID=9]
>> 0x3283500: i32 = Register %vreg5 [ID=1]
>> 0x3283710: i32 = Constant<3>...
2016 Mar 15
3
how to type-legalize a dag
...](align=4)> [ORD=8]
0x3ea4e20: <multiple use>
0x3ea44d8: i32 = Constant<0>
0x3ea4f28: ch,glue = CopyToReg 0x3ea4d18, 0x3ea4e20, 0x3ea44d8 [ORD=9]
0x3ea4f28: <multiple use>
0x3ea4e20: <multiple use>
0x3ea4f28: <multiple use>
0x3ea5030: ch = EsenciaISD::RET_FLAG 0x3ea4f28, 0x3ea4e20, 0x3ea4f28:1
[ORD=9]
Optimized lowered selection DAG: BB#0 'main:entry'
SelectionDAG has 14 nodes:
0x3e7e2f0: ch = EntryToken
0x3ea45e0: i32 = undef
0x3e7e2f0: <multiple use>
0x3ea43d0: i32 = FrameIndex<1>
0x3ea45e0: <multip...
2016 Mar 23
1
interpretation of dag output
...gt; [ID=-3]
0x26757e8: i32 = extract_vector_elt 0x2675da8, 0x26721e0 [ORD=9] [ID=-3]
0x26755d8: ch,glue = CopyToReg 0x2671fd0, 0x2672600, 0x26757e8 [ORD=13]
[ID=-3]
0x26755d8: <multiple use>
0x2672600: <multiple use>
0x26755d8: <multiple use>
0x26750b0: ch = EsenciaISD::RET_FLAG 0x26755d8, 0x2672600, 0x26755d8:1
[ORD=13] [ID=-3]
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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2016 Feb 04
2
New register class and patterns
...se a problem? In other words, since there is no output register, why
would LLVM start complaining. Below I'm repeating some code for reference.
Any help is appreciated.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32...
2016 Feb 03
2
New register class and patterns
On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
> On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote:
>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> I think for setting an implicit register, you still need to have 1 result
> here.
>
> If you look at