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2015-07-08 17:58 GMT+02:00 escha <escha at apple.com>: > [...] > > If you want to “revert" this sort of thing, you can do it at Select() time > or PreprocessISelDAG(), which is what I did on an out-of-tree backend to > turn add X, -C into sub X, C on selection time. This still lets all the > intermedi...

Hi Escha, We certainly would love to generalize them as long as the performance doesn't suffer in general. If you have specific use cases that are regressed due to these optimizations, I am more than happy to take a look. On Mon, Aug 24, 2015 at 6:43 PM, escha <escha at apple.com> wrote: > &...

...as one use is going to be the instruction we are going to remove anyway, right? I don’t think this is strictly true, but someone correct me if I’m wrong: if you have %y = add i32 %x, %x %x will have two uses, but it will have zero if %y is deleted. This was the corner case I was worried about. —escha -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150913/5ace6ad5/attachment.html>

...disjoint function in our backend is like 50 lines of code to cover all the cases), but a few of them are slightly more complex than “address space A can’t alias B”, so having a generic callback might be nicer and more powerful than a “does address space A alias address space B” callback, I think. —escha

I was lost from the thread at some point. Making the interface more general sounds good to me. This helps to solve Escha's concern that targets can know more about aliasing than just comparing address spaces. If there are no objections, I'll 1) add a new interface to TTI such as isTriviallyDisjoint. It returns false by default. 2) create a new AA that checks this interface, and add it to the AA chain. It cou...

Good point. The same argument seems to apply to copy() too so I suppose it depends how strict we want to be about it. From: fglaser at apple.com [mailto:fglaser at apple.com] On Behalf Of escha at apple.com Sent: 11 April 2016 20:55 To: Daniel Sanders Cc: Alex Rosenberg; llvm-dev at lists.llvm.org; Carlos Liam Subject: Re: [llvm-dev] Implementing a proposed InstCombine optimization On Apr 11, 2016, at 4:23 AM, Daniel Sanders <Daniel.Sanders at imgtec.com<mailto:Daniel.Sanders at i...

Hi Escha, Great to have your comment! Do you have any specific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case,...

...can share, but I imagine any similar test suite put through a typical compiler pipeline will exercise ADCE in similar ways. ADCE’s cost is pretty much the sum of (cost of managing the set) + (cost of eraseinstruction), which in our case turns out to be 1/3 the former and 2/3 the latter (roughly). —escha > On Sep 15, 2015, at 6:50 PM, Daniel Berlin <dberlin at dberlin.org> wrote: > > Can someone provide the file used to demonstrate the speedup here? > I'd be glad to take a quick crack at seeing if i can achieve the same speedup. > > > On Tue, Sep 15, 2015 at 2:16...

...on-small array and using better algorithms. Linear searching a 128 member array == slow I bet if you change the 128 to 8, you will see significant speedups. On Mon, Sep 14, 2015 at 11:23 AM, Steve King via llvm-dev <llvm-dev at lists.llvm.org> wrote: > On Mon, Sep 14, 2015 at 9:37 AM, escha via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Are there any other passes that could benefit from having a single bit (or similarly small amount) of per-Instruction metadata local to the pass, i.e. to avoid having to keep a side-Set of instructions... > > FWIW, I have a...

I have IR at https://ghostbin.com/paste/daxv5 <https://ghostbin.com/paste/daxv5> which is meant to exit 1, but it is always exiting 0. I'm using it as a template for checking if two functions @test1 and @test2 are equivalent by checking against the exhaustive possible i16 values. For this particular example it should be enough to know that for certain i16, @test1 and @test2 are *not*

...; SGTM +1 -Hal > > On Wed, Aug 12, 2015 at 12:00 PM, Jingyue Wu via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > I was lost from the thread at some point. > > > > Making the interface more general sounds good to me. This helps to > > solve > > Escha's concern that targets can know more about aliasing than just > > comparing address spaces. > > > > If there are no objections, I'll > > 1) add a new interface to TTI such as isTriviallyDisjoint. It > > returns false > > by default. > > 2) create a...

Thanks for your reply, escha, Yes, -loop-rorate makes it work. Regards, Xiangyang 2015-12-01 12:48 GMT-05:00 <escha at apple.com>: > > > On Dec 1, 2015, at 9:30 AM, Xiangyang Guo via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, All, > > > > Suppose I define on...

Dear all, I have been working on a new LLVM backend. Some instructions, like sub, can take an positive constante, encoded into 5 bits thus lower than 32, and a register, as operands. Unfortunately, DAGCombiner.cpp changes patterns like 'sub x, 5' into 'add x,-5'. Similarly, I found changes in some IR to IR passes, with no clear gain (at least not clear to me), and even penalty

...r-Instruction metadata local to the pass, i.e. to avoid having to keep a side-Set of instructions that’s only used to test membership of the set (i.e. not iterated over)? Is this sort of thing something reasonable (maybe it could be stuffed in the SubclassData short and exposed via a public API?) —escha

...dom values, then calls the function. 3. When the function returns, the wrapper checks the registers are the same, and if they’re not, bails to exit() and prints the invalid registers. This took a few dozen lines of code and worked entirely within the language, so it didn’t need compiler support. —escha > On May 13, 2016, at 4:10 PM, Sanjoy Das via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi David, > > David Blaikie wrote: > > Yeah, that's sort of what I'd be wondering too. > > > > It seems like if the compiler does the right thing for exis...

> On Aug 20, 2015, at 10:22 AM, escha <escha at apple.com> wrote: > >> >> On Aug 20, 2015, at 9:59 AM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote: >> >>> >>> On Aug 20, 2015, at 9:46 AM, Steve King <steve at metrokings.com <mailto:ste...

I would assume that it’s just considered to be garbage. I feel like any sort of per-pass side data like this should come with absolute minimal contracts, to avoid introducing any more inter-pass complexity. —escha > On Sep 14, 2015, at 2:28 PM, Sean Silva <chisophugis at gmail.com> wrote: > > What is the contract between passes for the marker bit? I.e. do passes need to "clean up" the marker bit to a predetermined value after they run? (or they need to assume that it might be dirty...

I never thought I’d see the day when someone proposed treating the 6502 like a GPU… —escha > On Feb 12, 2016, at 6:30 AM, Bruce Hoult via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I think it would be sufficient to pick 8 or 16 pairs of zero page locations as the "registers". Who needs 128 registers, unless you're also doing inter-procedural register...

Hi, As you may have noticed, since last year, we (Google's CUDA compiler team) have contributed quite a lot to the effort of optimizing LLVM for CUDA programs. I think it's worthwhile to write some docs to wrap them up for two reasons. 1) Whoever wants to understand or work on these optimizations has some detailed docs instead of just source code to refer to. 2) RFC on how to improve

...That's what I thought but I got the same error with: > > DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, > DAG.getTargetConstant(Intrinsic::my_intrinsic, DL, MVT::i16), LHS); > > Thanks. > > What should this call look like? > > > On Fri, Jun 24, 2016 at 10:53 AM, <escha at apple.com> wrote: > >> The intrinsic ID is an int, not a float. >> >> —escha >> >> On Jun 24, 2016, at 7:49 AM, Ryan Taylor via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >> given the following C code: >> >> float b...