Displaying 5 results from an estimated 5 matches for "errval".
2006 Apr 18
0
configure sys/audit.h WARNING
...ot; rather than "long long" worked
around the problem, so don't panic about that. (Via what is probably
preprocessor magic, strtoll() returns "long" on this system anyway.)
But I did look at the compiler output for strtonum.c, and the beginning
is kind of ugly. The struct errval ev[4] could really stand to be
declared static. And const. With some alternative hack to preserve
errno if there is no error.
Anyway, thanks for a great tool!
2012 Mar 19
24
[PATCHv2 00/11] arm: pass a device tree to dom0
This series of patches makes Xen pass a (somewhat) valid device tree
to dom0. The device tree for dom0 is the same as the one supplied to
Xen except the memory and chosen nodes are adjusted appropriately.
We don''t yet make use of the device tree to map MMIO regions or setup
interrupts for the guest and we still include the UART used for Xen''s
console.
Note that loading Linux
2013 Jul 25
19
[PATCH hivex 00/19] Fix read/write handling of li-records.
This is, hopefully, a full fix for handling of li-records.
See:
https://bugzilla.redhat.com/show_bug.cgi?id=717583
https://bugzilla.redhat.com/show_bug.cgi?id=987463
Rich.
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi,
here is the next version of changes to enable Linux to run as an SEV-ES
guest. The code was rebased to v5.7-rc3 and got a fair number of changes
since the last version.
What is SEV-ES
==============
SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted
State' and means a hardware feature of AMD processors which hides the
register state of VCPUs to the hypervisor by
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi,
here is the next version of changes to enable Linux to run as an SEV-ES
guest. The code was rebased to v5.7-rc3 and got a fair number of changes
since the last version.
What is SEV-ES
==============
SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted
State' and means a hardware feature of AMD processors which hides the
register state of VCPUs to the hypervisor by