search for: error_state

...has RESET=1 and the # post-reset event has ERROR=0. # Disable freeze hook. SUBSYSTEM=="drm", ACTION=="change", ENV{ERROR}=="1", RUN+="/usr/share/apport/apport-gpu-error-intel.py" The python script copies dmesg, Xorg.0.log, and /sys/kernel/debug/dri/0/i915_error_state. The latter is an intel-specific error dump they use to help diagnose bugs. We also capture a variety of other data and files, but those three seem to be what the devs want, mostly. We extract a couple error codes from the error_state file to use as a way of automatically detecting dupes. Here...

...nt; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = 4096; + new->error_state = pci_channel_io_normal; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), + busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + pci_read_config_byte(new, PCI_REVISION_ID, &new->...

...nt; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = 4096; + new->error_state = pci_channel_io_normal; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), + busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + pci_read_config_byte(new, PCI_REVISION_ID, &new->...

...nt; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = 4096; + new->error_state = pci_channel_io_normal; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), + busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + pci_read_config_byte(new, PCI_REVISION_ID, &new->...

...= pb->sysdata; + vf->dev.parent = pf->dev.parent; + vf->dev.bus = pf->dev.bus; + vf->devfn = devfn; + vf->hdr_type = PCI_HEADER_TYPE_NORMAL; + vf->multifunction = 0; + vf->vendor = pf->vendor; + vf->device = pf->iov->device; + vf->cfg_size = 4096; + vf->error_state = pci_channel_io_normal; + vf->pcie_type = PCI_EXP_TYPE_ENDPOINT; + vf->dma_mask = 0xffffffff; + + dev_set_name(&vf->dev, "%04x:%02x:%02x.%d", pci_domain_nr(pb), bus, + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + pci_read_config_byte(vf, PCI_REVISION_ID, &vf->revision...

...= pb->sysdata; + vf->dev.parent = pf->dev.parent; + vf->dev.bus = pf->dev.bus; + vf->devfn = devfn; + vf->hdr_type = PCI_HEADER_TYPE_NORMAL; + vf->multifunction = 0; + vf->vendor = pf->vendor; + vf->device = pf->iov->device; + vf->cfg_size = 4096; + vf->error_state = pci_channel_io_normal; + vf->pcie_type = PCI_EXP_TYPE_ENDPOINT; + vf->dma_mask = 0xffffffff; + + dev_set_name(&vf->dev, "%04x:%02x:%02x.%d", pci_domain_nr(pb), bus, + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + pci_read_config_byte(vf, PCI_REVISION_ID, &vf->revision...

...= pb->sysdata; + vf->dev.parent = pf->dev.parent; + vf->dev.bus = pf->dev.bus; + vf->devfn = devfn; + vf->hdr_type = PCI_HEADER_TYPE_NORMAL; + vf->multifunction = 0; + vf->vendor = pf->vendor; + vf->device = pf->iov->device; + vf->cfg_size = 4096; + vf->error_state = pci_channel_io_normal; + vf->pcie_type = PCI_EXP_TYPE_ENDPOINT; + vf->dma_mask = 0xffffffff; + + dev_set_name(&vf->dev, "%04x:%02x:%02x.%d", pci_domain_nr(pb), bus, + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + pci_read_config_byte(vf, PCI_REVISION_ID, &vf->revision...

...fn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = PCI_CFG_SPACE_EXP_SIZE; + new->error_state = pci_channel_io_normal; + new->dma_mask = 0xffffffff; + + sprintf(pci_name(new), "%04x:%02x:%02x.%d", pci_domain_nr(bus), + busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + new->class = dev->class; + new->current_state = PCI_UNKNOWN; +...

...fn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = PCI_CFG_SPACE_EXP_SIZE; + new->error_state = pci_channel_io_normal; + new->is_pcie = 1; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), + busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));...

...fn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = PCI_CFG_SPACE_EXP_SIZE; + new->error_state = pci_channel_io_normal; + new->is_pcie = 1; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), + busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));...

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. [PATCH 1/8 v4] PCI: define PCI resource names in a 'enum' [PATCH 2/8 v4] PCI: export __pci_read_base

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. [PATCH 1/8 v4] PCI: define PCI resource names in a 'enum' [PATCH 2/8 v4] PCI: export __pci_read_base

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. Major changes between v4 -> v5: 1, remove interfaces for PF driver to create sysfs entries (Matthew

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. Major changes between v4 -> v5: 1, remove interfaces for PF driver to create sysfs entries (Matthew

https://bugs.freedesktop.org/show_bug.cgi?id=50121 Bug #: 50121 Summary: [Regression] NV34 Fx5200 fails to resume with commit 5d720f2450 Classification: Unclassified Product: xorg Version: git Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: normal Priority:

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. Changes from v5 to v6: 1, update ABI document to include SR-IOV sysfs entries (Greg KH) 2, fix two coding

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. Changes from v5 to v6: 1, update ABI document to include SR-IOV sysfs entries (Greg KH) 2, fix two coding