Displaying 1 result from an estimated 1 matches for "ep2s60f672c5es".
2006 Jun 05
0
Idct - fpga - improved
...ing the latency of samples (number of clock cycles
needed to decode a data sample).
Report:
--------------
Fitter Status : Successful - Mon Jun 5 16:38:21 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ
Revision Name : idctslow
Top-level Entity Name : IDctSlow
Family : Stratix II
Device : EP2S60F672C5ES
Timing Models : Final
Total ALUTs : 2,538 / 48,352 ( 5 % )
Total registers : 466
Total pins : 54 / 493 ( 11 % )
Total virtual pins : 0
Total memory bits : 3,072 / 2,544,192 ( < 1 % )
DSP block 9-bit elements : 2 / 288 ( < 1 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
--...