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BIll, Thanks. I am seeing some problems here, for example when all the fields are missing, or all the fields in a row are missing. I've fixes for those, and will commit to R-devel shortly. On Tue, 17 Jul 2007, bill at insightful.com wrote: > Full_Name: Bill Dunlap > Version: 2.5.0 > OS: Red Hat Enterprise Linux WS release 3 (Taroon Update 6) > Submission from: (NULL)

Full_Name: Bill Dunlap Version: 2.5.0 OS: Red Hat Enterprise Linux WS release 3 (Taroon Update 6) Submission from: (NULL) (24.17.60.30) If you read a dcf file with read.dcf(file,fields=c("Field",...)) and the file does not contain the desired field "Field", read.dcf puts a character NA for that entry in its output matrix. If you then call write.dcf, passing it the output of

...orrs r12, r2, r3, lsr #1 ^~~~ /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:58:5: error: invalid instruction mnemonic 'it' it ne ^~ /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:59:5: error: invalid instruction mnemonic 'eorsne' eorsne r12, r0, r1 ^~~~~~ /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:61:5: error: invalid instruction mnemonic 'it' it pl ^~ /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:62:5: error: invalid instruction mnemo...

Dear R-Help, I am trying to perform forward selection on the following coxph model: >my.bpfs <- Surv(bcox$pfsdays, bcox$pfscensor) > b.cox <- coxph(my.bpfs ~ Cbase + Abase + Cbave + CbSD + KPS + gender + as.factor(eor) + Age)>stepAIC(b.cox, scope=list(upper =~ Cbase + Abase + Cbave + CbSD + KPS + gender + as.factor(eor) + Age, lower=~1), direction= c("forward")) However

I am currently trying to compile a pretty simple program to work on an experimental board. It contains an (FPGA-version of) an ARMv4 processor. So basically, I try this (on my Ubuntu 18.04.1 LTS): clang -v --target=arm-none-eabi -c barehello.c -o barehelloCLANG.o clang -v --target=arm-none-eabi -c io.c -o io.o clang -v --target=arm-none-eabi barehelloCLANG.o io.o -o helloCLANGstatic -static

...>> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:58:5: error: invalid instruction mnemonic 'it' >> it ne >> ^~ >> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:59:5: error: invalid instruction mnemonic 'eorsne' >> eorsne r12, r0, r1 >> ^~~~~~ >> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:61:5: error: invalid instruction mnemonic 'it' >> it pl >> ^~ >> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm...

...>> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:58:5: error: invalid instruction mnemonic 'it' >> it ne >> ^~ >> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:59:5: error: invalid instruction mnemonic 'eorsne' >> eorsne r12, r0, r1 >> ^~~~~~ >> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:61:5: error: invalid instruction mnemonic 'it' >> it pl >> ^~ >> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm...

...gt; > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:58:5: error: invalid instruction mnemonic 'it' > > it ne > > ^~ > > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:59:5: error: invalid instruction mnemonic 'eorsne' > > eorsne r12, r0, r1 > > ^~~~~~ > > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:61:5: error: invalid instruction mnemonic 'it' > > it pl > > ^~ > > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/a...

Hey everyone. My mind has been boggled by an issue I ran into a few hours ago. I am completely lost as to why the following code behaves the way it does and would appreciate any hints from you guys. It would already be super-helpful if others could post their output for the following so that I can figure out whether this is weirdness specific to my setup or a global phenomenon. So far,

I was wondering if there was a way to recompile ogg123 so that it didnt look for "Ogg" at the start of each file. Ie change it so it looked for "Dog" or something. Why you ask? because in theory Im not ment to have any music files on my work computer NFI why but just cant. If I could mask an ogg file to look like another file then I could beat the system. Assuming that they

...vm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:58:5: error: invalid instruction mnemonic 'it' > >>> it ne > >>> ^~ > >>> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:59:5: error: invalid instruction mnemonic 'eorsne' > >>> eorsne r12, r0, r1 > >>> ^~~~~~ > >>> /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:61:5: error: invalid instruction mnemonic 'it' > >>> it pl > >>> ^~ > >>> /ho...

...1 > ^~~~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:58:5: error: invalid instruction mnemonic 'it' > it ne > ^~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:59:5: error: invalid instruction mnemonic 'eorsne' > eorsne r12, r0, r1 > ^~~~~~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:61:5: error: invalid instruction mnemonic 'it' > it pl > ^~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:62:5: erro...

Hello everyone At EuroLLVM I presented some testing work we have been doing on improving correctness of the MC Layer for ARM. There seemed to be interest from the community in seeing the results of this test suite. Background ----------- We are using a test suite, called MC Hammer, that compares MC with an ARM in-house implementation of the same functionality. The test space for this suite is

...1 > ^~~~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:58:5: error: invalid instruction mnemonic 'it' > it ne > ^~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:59:5: error: invalid instruction mnemonic 'eorsne' > eorsne r12, r0, r1 > ^~~~~~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:61:5: error: invalid instruction mnemonic 'it' > it pl > ^~ > /home/llvm_all/llvm/projects/compiler-rt/lib/builtins/arm/comparesf2.S:62:5: erro...

...g-only=regcoalescing to see what is going wrong. If you want to take a look at this yourself, the issue is easy to reproduce with Thumb1: $ cat > test.c typedef unsigned long long t; t foo(t a, t b) { t a4 = b^a^18; return a4; } $ clang -cc1 -triple thumbv5-u-u -S -O2 test.c -o - [...] eors r1, r3 mov r3, r0 eors r3, r2 movs r0, #18 eors r0, r3 bx lr [...] -Eli

Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) have similar patterns, as we would expect: defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node: $RHS))>>; defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node: $RHS))>>; Compiling the following three works as expected: %tmp1 = xor i32

I've seen this posting before but I need to get a grasp on this. I am using winbindd for users that don't have a local account on a Linux box. I thought that placing the entries below in the smb.conf would create users in ou=Idmap. Instead the ou=Idmap increments the uidNumber with every user that is added,but the user ID mappings are stored in /usr/local/var/locks/winbindd_idmap.tdb. What

On Jun 25, 2009, at 4:38 PM, David Goodwin wrote: > Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) > have similar patterns, as we would expect: > > defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node: > $RHS))>>; > defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node: >

Hi Borja, > Without doing what i mentioned and letting LLVM expand all operations wider > than 8 bits as you asked, the code produced is excellent supposing that many > of the moves there should be 16 bit moves reducing code size and right > register allocation, also something important for me is that the code is > better than gcc's. When i say right reg allocation it doesnt

...vector_und +.swi: .long vector_swi +.pabt: .long vector_pabt +.dabt: .long vector_dabt +.adx: .long vector_reserved +.irq: .long vector_irq +.fiq: .long vector_fiq + + .align 5 +vector_reset: +1: + b 1b + + .align 5 +vector_irq: + SAVE_CONTEXT 0x18, 4 + + mrs r0, spsr + and r0, r0, #PSR_MODE_MASK + eors r0, r0, #PSR_MODE_SVC + + bne return_to_guest + + cpsid i + + RESTORE_CONTEXT + + .align 5 +vector_dabt: + str r0, [sp, #-16] + str lr, [sp, #-12] + mrs r0, spsr + str r0, [sp, #-8] + sub r0, sp, #16 + + msr cpsr_cxsf, #(PSR_I_BIT | PSR_F_BIT | PSR_MODE_SVC) + + sub sp, sp, #CTX...