Displaying 2 results from an estimated 2 matches for "eorrr".
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corrr
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
...[maystore] [attdialect], $0:[regdef-ec:GPRPair],
%R8_R9<earlyclobber,def>, $1:[reguse:GPR], %R4, <!3>
%R0<def> = ANDri %R7, 1, pred:14, pred:%noreg, opt:%CPSR<def>
%R0<def> = MOVr %LR, pred:1, pred:%CPSR<kill>, opt:%noreg
%R1<def> = EORrr %R0, %LR, pred:14, pred:%noreg, opt:%noreg
%R1<def> = ANDrr %R9, %R1<kill>, pred:14, pred:%noreg, opt:%noreg
%R2<def> = ADDrr %R8, %R2<kill>, pred:14, pred:%noreg, opt:%CPSR<def>
%R3<def> = ADCrr %R9, %R3<kill>, pred:14, pred:%noreg,...
2018 Apr 05
1
A9 Scheduler
...-----------------------------------------------===//
// Subtarget-specific overrides. Map opcodes to list of SchedReadWrite
types.
//
def : InstRW< [WriteALU],
(instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr",
"EORrr",
"BICrr")>;
This same instruction is defined in the ARMInstrInfo.td as inheriting from
AsI1_bin_irs (shown below) which, in turn, associates Sched<[WriteALU,
ReadALU]> with the instruction.
defm AND : AsI1_bin_irs<0b0000, "and",...