search for: eng3d

...0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info) } else if (!nv50_2d_src_format_faithful(info->src.format)) { if (!util_format_is_luminance(info->src.format)) { + if (!nv50_2d_dst_format_ops_supported(info->dst.format)) + eng3d = TRUE; + else if (util_format_is_intensity(info->src.format)) eng3d = info->src.format != PIPE_FORMAT_I8_UNORM; else - if (!nv50_2d_dst_format_ops_supported(info->dst.format)) - eng3d = TRUE; + if (ut...

...uint result = *idx; > > - if (sem == TGSI_SEMANTIC_GENERIC && result >= 8) { > - for (result = 0; result < 8; result++) { > - if (fp->texcoord[result] == *idx) { > + if (sem == TGSI_SEMANTIC_GENERIC) { > + uint num_texcoords = (screen->eng3d->oclass < NV40_3D_CLASS) ? 8 : 10; > + for (result = 0; result < num_texcoords; result++) { > + if (fp->texcoord[result] == *idx + 8) { maybe i'm too tired, but why exactly *idx + 8 ? > + sem = TGSI_SEMANTIC_TEXCOORD; > emit = vrout...

...- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -407,8 +407,6 @@ nvc0_screen_destroy(struct pipe_screen *pscreen) FREE(screen->tic.entries); - nouveau_mm_destroy(screen->mm_VRAM_fe0); - nouveau_object_del(&screen->eng3d); nouveau_object_del(&screen->eng2d); nouveau_object_del(&screen->m2mf); @@ -1027,7 +1025,6 @@ nvc0_screen_create(struct nouveau_device *dev) mm_config.nvc0.tile_mode = 0; mm_config.nvc0.memtype = 0xfe0; - screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_...

...- if (sem == TGSI_SEMANTIC_GENERIC && result >= 8) { >>> - for (result = 0; result < 8; result++) { >>> - if (fp->texcoord[result] == *idx) { >>> + if (sem == TGSI_SEMANTIC_GENERIC) { >>> + uint num_texcoords = (screen->eng3d->oclass < NV40_3D_CLASS) ? 8 : >>> 10; >>> + for (result = 0; result < num_texcoords; result++) { >>> + if (fp->texcoord[result] == *idx + 8) { >> >> maybe i'm too tired, but why exactly *idx + 8 ? > See nvfx_fragprog.c: > &g...

...s the drivers, one file per the commit. A new "nvfx" directory is created, and unified files are put there one by one. After all patches are applied, the nv30 and nv40 directories are removed and the only the new nvfx directory remains. The first patches unify the engine naming (s/curie/eng3d/g; s/rankine/eng3d), and switch nv40 to use the NV34TCL_ constants. Initial versions of this work changed renouveau.xml to create a new "NVFXTCL" object, but the current version doesn't need any renouveau.xml modification at all. The "unification+fixes" branch referenced ab...

...au/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -219,7 +219,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return 0; case PIPE_SHADER_CAP_MAX_INPUTS: - return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10; + return (eng3d->oclass >= NV40_3D_CLASS) ? 10 : 8; case PIPE_SHADER_CAP_MAX_CONSTS: return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32; case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: -- 1.8.3.2

This makes the vertex buffer go to GART, not VRAM, and redoes the mapping to not use the UNSYNCHRONIZED access (which is meaningless on a VRAM buffer anyways). While we're at it, add some flushes for VBO data. Moving the vertex buffer from VRAM to GART makes glxgears work fully with NV30_SWTNL=1. The other changes just seem like a good idea. I'm not sure *why* moving the buffer from VRAM

Hi All, Here is a bunch of fixes for nv30 cards, the first patch is a resend of a patch I send a while back. AFAICT that one is ready for merging, but it is not entirely clear to me what the process is for getting (nouveau) mesa patches merged. Should I request commit rights, and push my own patches once they have been reviewed ? Regards, Hans

...pipe_screen *pscreen, > unsigned sample_count, > unsigned bindings) > { > - if (sample_count > 4) > - return false; > + struct nv30_screen *screen = nv30_screen(pscreen); > + > + if (screen->eng3d->oclass >= NV40_3D_CLASS) { > + if (sample_count > 4) > + return false; > + } else { > + if (sample_count > 0) > + return false; > + } > + > if (!(0x00000017 & (1 << sample_count))) > return false; > > -...

This patch series silences some unknown cap warnings and fixes up coding style (patch 1+4). The most important part of this series are the two patches in the middle. They rework the state_fb code, so that we are able to render to not 64 byte aligned targets, as this is the only real use-case for render temporaries this allows us to drop temp code completely and simplifies a lot

...src->ms_y << 32; + srcx += (int64_t)1 << (src->ms_x + 31); + srcy += (int64_t)1 << (src->ms_y + 31); } dstx = info->dst.box.x << dst->ms_x; @@ -1438,8 +1438,8 @@ nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info) eng3d = TRUE; /* FIXME: can't make this work with eng2d anymore */ - if (info->src.resource->nr_samples > 1 || - info->dst.resource->nr_samples > 1) + if ((info->src.resource->nr_samples | 1) != + (info->dst.resource->nr_samples | 1)) eng3d =...

.../nvc0_screen.c > +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > @@ -407,8 +407,6 @@ nvc0_screen_destroy(struct pipe_screen *pscreen) > > FREE(screen->tic.entries); > > - nouveau_mm_destroy(screen->mm_VRAM_fe0); > - > nouveau_object_del(&screen->eng3d); > nouveau_object_del(&screen->eng2d); > nouveau_object_del(&screen->m2mf); > @@ -1027,7 +1025,6 @@ nvc0_screen_create(struct nouveau_device *dev) > > mm_config.nvc0.tile_mode = 0; > mm_config.nvc0.memtype = 0xfe0; > - screen->mm_VRAM_fe0 = n...

...um/drivers/nouveau/nvc0/nvc0_screen.c > > @@ -407,8 +407,6 @@ nvc0_screen_destroy(struct pipe_screen *pscreen) > > > > FREE(screen->tic.entries); > > > > - nouveau_mm_destroy(screen->mm_VRAM_fe0); > > - > > nouveau_object_del(&screen->eng3d); > > nouveau_object_del(&screen->eng2d); > > nouveau_object_del(&screen->m2mf); > > @@ -1027,7 +1025,6 @@ nvc0_screen_create(struct nouveau_device *dev) > > > > mm_config.nvc0.tile_mode = 0; > > mm_config.nvc0.memtype = 0xfe0; >...

...allium/drivers/nouveau/nvc0/nvc0_screen.c > @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev) > PUSH_DATAh(push, screen->txc->offset); > PUSH_DATA (push, screen->txc->offset); > PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); > + if (screen->eng3d->oclass >= GM107_3D_CLASS) { > + screen->tic.maxwell = true; > + if (screen->eng3d->oclass == GM107_3D_CLASS) { > + screen->tic.maxwell = > + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true); > + IMMED_NVC0(push, SUBC...

...u/nv30/nv30_context.c index 2146d27..4f68eee 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_context.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_context.c @@ -235,7 +235,6 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv) /*XXX: nvfx... */ nv30->is_nv4x = (screen->eng3d->oclass >= NV40_3D_CLASS) ? ~0 : 0; - nv30->use_nv4x = (screen->eng3d->oclass >= NV40_3D_CLASS) ? ~0 : 0; nv30->render_mode = HW; nv30->sample_mask = 0xffff; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.h b/src/gallium/drivers/nouveau/nv30/nv30_cont...

But at the time the mesa3d file src/gallium/drivers/nouveau/nv30/nv30_screen.c is called and when the various PUSH_DATA begin to be called there is not yet a call to nouveau_pushbuf_space. So it would generate a seg fault in push->curr. Again, sorry for the confusion and thanks for the reply. Awaiting for an answer if possible. Thanks in advance. 2015-11-02 14:44 GMT-03:00 Ilia Mirkin

...nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev) PUSH_DATAh(push, screen->txc->offset); PUSH_DATA (push, screen->txc->offset); PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); + if (screen->eng3d->oclass >= GM107_3D_CLASS) { + screen->tic.maxwell = true; + if (screen->eng3d->oclass == GM107_3D_CLASS) { + screen->tic.maxwell = + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true); + IMMED_NVC0(push, SUBC_3D(0x0f10), screen->t...

This series is to allow NVIDIA chips with shared memory to operate more efficiently (and to operate at all once we disable VRAM from the kernel driver) by allowing nouveau_screen to specify a domain to use for objects originally allocated into VRAM. If the domain is not overridden, the default NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be used in place of

...au/nvc0/nvc0_screen.c >> @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev) >> PUSH_DATAh(push, screen->txc->offset); >> PUSH_DATA (push, screen->txc->offset); >> PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); >> + if (screen->eng3d->oclass >= GM107_3D_CLASS) { >> + screen->tic.maxwell = true; >> + if (screen->eng3d->oclass == GM107_3D_CLASS) { >> + screen->tic.maxwell = >> + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true); >> + I...

...fo.dst.resource->nr_samples <= 1 && > !util_format_is_depth_or_stencil(info.src.resource->format) && > !util_format_is_pure_integer(info.src.resource->format)) { > - nv30_resource_resolve(nv30, blit_info); > + if (nv30->screen->eng3d->oclass >= NV40_3D_CLASS) > + nv40_resource_resolve(nv30, blit_info); > + else > + nv30_resource_resolve(nv30, blit_info); > return; > } > > -- > 2.4.3 >