search for: endpoint_start

...TIO_IOMMU_TOPO_ENDPOINT (1)] struct virtio_iommu_topo_endpoint +\end{description} + +\paragraph{PCI range}\label{sec:Device Types / IOMMU Device / Device initialization / topology / PCI range} + +\begin{lstlisting} +struct virtio_iommu_topo_pci_range { + struct virtio_iommu_topo_head head; + le32 endpoint_start; + le16 hierarchy; + le16 requester_start; + le16 requester_end; + le16 reserved; +}; +\end{lstlisting} + +The PCI range structure describes the endpoint IDs of a series of PCI +devices. + +\begin{description} + \item[\field{hierarchy}] Identifier of the PCI hierarchy. Sometimes + called PC...

...se_topology); > + > +/* > + * Return true if the device matches this topology structure. Write the endpoint > + * ID into epid if it's the case. > + */ > +static bool viommu_parse_pci(struct pci_dev *pdev, union viommu_topo_cfg *cfg, > + u32 *epid) > +{ > + u32 endpoint_start; > + u16 start, end, domain; > + u16 devid = pci_dev_id(pdev); > + u16 type = le16_to_cpu(cfg->type); > + > + if (type != VIRTIO_IOMMU_TOPO_PCI_RANGE) > + return false; > + > + start = le16_to_cpu(cfg->pci.requester_start); > + end = le16_to_cpu(cfg->pci.reque...

...y); > + > +/* > + * Return true if the device matches this topology structure. Write the > endpoint > + * ID into epid if it's the case. > + */ > +static bool viommu_parse_pci(struct pci_dev *pdev, union > viommu_topo_cfg *cfg, > + u32 *epid) > +{ > + u32 endpoint_start; > + u16 start, end, domain; > + u16 devid = pci_dev_id(pdev); > + u16 type = le16_to_cpu(cfg->type); > + > + if (type != VIRTIO_IOMMU_TOPO_PCI_RANGE) > + return false; > + > + start = le16_to_cpu(cfg->pci.requester_start); > + end = le16_to_cpu(cfg->pci.reque...

...y); > + > +/* > + * Return true if the device matches this topology structure. Write the > endpoint > + * ID into epid if it's the case. > + */ > +static bool viommu_parse_pci(struct pci_dev *pdev, union > viommu_topo_cfg *cfg, > + u32 *epid) > +{ > + u32 endpoint_start; > + u16 start, end, domain; > + u16 devid = pci_dev_id(pdev); > + u16 type = le16_to_cpu(cfg->type); > + > + if (type != VIRTIO_IOMMU_TOPO_PCI_RANGE) > + return false; > + > + start = le16_to_cpu(cfg->pci.requester_start); > + end = le16_to_cpu(cfg->pci.reque...

...ay describes either a PCI range or a single MMIO endpoint, and their associated endpoint IDs: struct virtio_iommu_topo_pci_range { __le16 type; /* 1: PCI range */ __le16 hierarchy; /* PCI domain number */ __le16 requester_start; /* First BDF */ __le16 requester_end; /* Last BDF */ __le32 endpoint_start; /* First endpoint ID */ }; struct virtio_iommu_topo_endpoint { __le16 type; /* 2: Endpoint */ __le16 reserved; /* 0 */ __le32 endpoint; /* Endpoint ID */ __le64 address; /* First MMIO address */ }; You can find the QEMU patches based on Eric's latest device on my virtio-iommu/deve...

...y); > + > +/* > + * Return true if the device matches this topology structure. Write the > endpoint > + * ID into epid if it's the case. > + */ > +static bool viommu_parse_pci(struct pci_dev *pdev, union > viommu_topo_cfg *cfg, > + u32 *epid) > +{ > + u32 endpoint_start; > + u16 start, end, domain; > + u16 devid = pci_dev_id(pdev); > + u16 type = le16_to_cpu(cfg->type); > + > + if (type != VIRTIO_IOMMU_TOPO_PCI_RANGE) > + return false; > + > + start = le16_to_cpu(cfg->pci.requester_start); > + end = le16_to_cpu(cfg->pci.reque...

...u_config) && ++iter < 0x10000) { + memset(&cap, 0, sizeof(cap)); + + cap.head.type = viommu_cread(dev, pci_cfg, dev_cfg, 2, offset); + cap.head.next = viommu_cread(dev, pci_cfg, dev_cfg, 2, offset + 2); + + switch (cap.head.type) { + case VIRTIO_IOMMU_TOPO_PCI_RANGE: + cap.pci.endpoint_start = viommu_cread(dev, pci_cfg, + dev_cfg, 2, offset + + 4); + cap.pci.hierarchy = viommu_cread(dev, pci_cfg, dev_cfg, + 2, offset + 8); + cap.pci.requester_start = viommu_cread(dev, pci_cfg, + dev_cfg, 2, + offset + 10); + cap.pci.request...

...ci_cfg, dev_cfg, 2, offset); > + cap.head.next = viommu_cread(dev, pci_cfg, dev_cfg, 2, offset + 2); All of this doesn't seem to be endian-clean. Try running sparse I think it will complain. > + > + switch (cap.head.type) { > + case VIRTIO_IOMMU_TOPO_PCI_RANGE: > + cap.pci.endpoint_start = viommu_cread(dev, pci_cfg, > + dev_cfg, 2, offset > + + 4); > + cap.pci.hierarchy = viommu_cread(dev, pci_cfg, dev_cfg, > + 2, offset + 8); > + cap.pci.requester_start = viommu_cread(dev, pci_cfg, > + dev_cfg, 2, > +...

I'm seeking feedback on multi-platform support for virtio-iommu. At the moment only devicetree (DT) is supported and we don't have a pleasant solution for other platforms. Once we figure out the topology description, x86 support is trivial. Since the IOMMU manages memory accesses from other devices, the guest kernel needs to initialize the IOMMU before endpoints start issuing DMA.

I'm seeking feedback on multi-platform support for virtio-iommu. At the moment only devicetree (DT) is supported and we don't have a pleasant solution for other platforms. Once we figure out the topology description, x86 support is trivial. Since the IOMMU manages memory accesses from other devices, the guest kernel needs to initialize the IOMMU before endpoints start issuing DMA.

...; > +}; > + > +#define VIRTIO_IOMMU_TOPO_PCI_RANGE 0x1 > +#define VIRTIO_IOMMU_TOPO_ENDPOINT 0x2 > + > +struct virtio_iommu_topo_pci_range { > + __le16 type; > + __le16 hierarchy; > + __le16 requester_start; > + __le16 requester_end; > + __le32 endpoint_start; > +}; > + > +struct virtio_iommu_topo_endpoint { > + __le16 type; > + __le16 reserved; > + __le32 endpoint; > + __le64 address; > }; > > /* Request types */ As any UAPI change, this needs to be copied to virtio TC. I believe an old version of QEM...

...+#define VIRTIO_IOMMU_TOPO_PCI_RANGE 0x1 +#define VIRTIO_IOMMU_TOPO_MMIO 0x2 + +struct virtio_iommu_topo_pci_range { + /* VIRTIO_IOMMU_TOPO_PCI_RANGE */ + __u8 type; + __u8 reserved; + /* Length of this structure */ + __le16 length; + /* First endpoint ID in the range */ + __le32 endpoint_start; + /* PCI domain number */ + __le16 segment; + /* PCI Bus:Device.Function range */ + __le16 bdf_start; + __le16 bdf_end; + __le16 padding; +}; + +struct virtio_iommu_topo_mmio { + /* VIRTIO_IOMMU_TOPO_MMIO */ + __u8 type; + __u8 reserved; + /* Length of this structure */ + _...

...spec->dev_id.type = VIRT_TOPO_DEV_TYPE_PCI; + spec->dev_id.segment = ioread16(&cfg->pci.segment); + spec->dev_id.bdf_start = ioread16(&cfg->pci.bdf_start); + spec->dev_id.bdf_end = ioread16(&cfg->pci.bdf_end); + spec->endpoint_id = ioread32(&cfg->pci.endpoint_start); + break; + case VIRTIO_IOMMU_TOPO_MMIO: + if (len < sizeof(cfg->mmio)) + goto err_free; + + spec->dev_id.type = VIRT_TOPO_DEV_TYPE_MMIO; + spec->dev_id.base = ioread64(&cfg->mmio.address); + spec->endpoint_id = ioread32(&cfg->mmio.endpoint); + break; + default...

...pe = VIRT_TOPO_DEV_TYPE_PCI; > + spec->dev_id.segment = ioread16(&cfg->pci.segment); > + spec->dev_id.bdf_start = ioread16(&cfg->pci.bdf_start); > + spec->dev_id.bdf_end = ioread16(&cfg->pci.bdf_end); > + spec->endpoint_id = ioread32(&cfg->pci.endpoint_start); > + break; > + case VIRTIO_IOMMU_TOPO_MMIO: > + if (len < sizeof(cfg->mmio)) > + goto err_free; > + > + spec->dev_id.type = VIRT_TOPO_DEV_TYPE_MMIO; > + spec->dev_id.base = ioread64(&cfg->mmio.address); > + spec->endpoint_id = ioread32(&cfg...

Add a topology description to the virtio-iommu driver and enable x86 platforms. Since [v2] we have made some progress on adding ACPI support for virtio-iommu, which is the preferred boot method on x86. It will be a new vendor-agnostic table describing para-virtual topologies in a minimal format. However some platforms don't use either ACPI or DT for booting (for example microvm), and will

Add a topology description to the virtio-iommu driver and enable x86 platforms. Since [v2] we have made some progress on adding ACPI support for virtio-iommu, which is the preferred boot method on x86. It will be a new vendor-agnostic table describing para-virtual topologies in a minimal format. However some platforms don't use either ACPI or DT for booting (for example microvm), and will