Displaying 8 results from an estimated 8 matches for "endloop0".
2013 Jun 26
1
[LLVMdev] Auxiliary operand types for disassembler.
...et to 01b and the parse bits in insn 2 are set to 10b then this is the
last packet in hardware loop 1. If the parse bits in insn 1 and insn 2
are both set to 10b then this is then end in both hardware loops 0 and
1. At the tail of the packet the disassembler would add the following:
}:endloop0
}:endloop1
}:endloop0:endloop1
to represent the end of the various loops.
The disassembler has to accumulate the MCInsts for the whole packet and
either the raw hex encodings or append the needed info as an operand
stored in the MCInst. The reason I tried using MCOperand is th...
2015 Apr 14
7
[LLVMdev] RFC building a target MCAsmParser
...many instructions
if(p1) r0 = add(r1, r2)
Dense semantics for DSP applications. Complex multiply optionally shifting
result left by 1 with optional rounding and optional saturation
r0 = cmpy(r1, r2):<<1:rnd:sat
Hardware loops ended by optional packet suffix
{ r0 = r1 }:endloop0:endloop1
We found the Hexagon grammar to be straight forward to implement using plain
lex / parse but harder within the MCTargetAsmParser.
We were thinking a way to get the grammar to work would involve modifying
tablegen and the main asm parser loop. We'd have to make tablegen break...
2013 Jun 25
0
[LLVMdev] Auxiliary operand types for disassembler.
Hi Sid,
This feels like it’s exposing too much of the disassembler internals into the MCOperand representation. I’m not sure I follow why that’s necessary. Can you elaborate a bit?
-Jim
On Jun 25, 2013, at 8:24 AM, Sid Manning <sidneym at codeaurora.org> wrote:
>
> I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type,
2020 Jan 14
3
[tablegen] table readability / performance
...clang and gcc, the compile-time for generated tables is
significantly reduced when emitting string literals, and the user can
grep the name tables without huge effort. The above table is now:
extern const char HexagonInstrNameData[] = {
/* 0 */ "G_FLOG10\0"
/* 9 */ "ENDLOOP0\0"
/* 18 */ "V6_vdd0\0"
/* 26 */ "PS_vdd0\0"
/* 34 */ "V6_ld0\0"
/* 41 */ "V6_zld0\0"
[...]
};
My question then is: Is there a specific technical reason that we should
avoid emitting concatenated string literals rather...
2013 Jun 25
2
[LLVMdev] Auxiliary operand types for disassembler.
I'm working on a disassembler for hexagon (vliw) architecture and I
would like to add an additional operand type, "kAux" to the MCOperand class.
The reason for this is that each insn has parse bits which are not
explicit operands and have differing meanings based on the insn's
location within the packet and the number of insns inside the packet.
In order for the disassembler
2019 Jun 30
6
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...t: 0, value: .LBB0_3, kind: fixup_Hexagon_B7_PCREL
.Ltmp0: // Block address taken
.LBB0_3: // %while.body
// =>This Inner Loop Header: Depth=1
{
r0 = memw(r2++#4)
memw(r1++#4) = r0.new
} :endloop0 // encoding: [0x20,0x80,0x82,0x9b,0x08,0xd2,0xa1,0xab]
// %bb.4: // %while.end
{
r31:30 = dealloc_return(r30):raw
} // encoding: [0x1e,0xc0,0x1e,0x96]
.LBB0_5: // %while.body.rtli
{...
2019 Jul 01
0
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...// %while.body
// =>This Inner Loop Header: Depth=1
{
r0 = memw(r2++#4)
memw(r1++#4) = r0.new
} :endloop0 // encoding: [0x20,0x80,0x82,0x9b,0x08,0xd2,0xa1,0xab]
// %bb.4: // %while.end
{
r31:30 = dealloc_return(r30):raw
} // enco...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...+ MCI.setEndPacket(Index == (Size-1));
>> +
>> + HexagonLowerToMC(BundleMIs[Index], MCI, *this);
>> + OutStreamer.EmitInstruction(MCI);
>> + }
>> + }
>> + else {
>> + HexagonMCInst MCI;
>> + if (MI->getOpcode() == Hexagon::ENDLOOP0) {
>> + MCI.setStartPacket(true);
>> + MCI.setEndPacket(true);
>> + }
>> + HexagonLowerToMC(MI, MCI, *this);
>> + OutStreamer.EmitInstruction(MCI);
>> + }
>>
>> return;
>> }
>> @@ -242,17 +277,17 @@ void HexagonAs...