Displaying 5 results from an estimated 5 matches for "end_loop_index".
2014 Oct 24
2
[LLVMdev] Virtual register def doesn't dominate all uses
...UL at this stage. Their "state" is LEGAL and not CUSTOM or EXPAND. But it fails with implemented operations as well.
What did I do wrong? Missing implementation for some operations? What did I miss to implement?
Thanks in advance,
Boris
----8<----
C source-code:
int simple_loop(int end_loop_index)
{
int sum = 0;
for(int i = 0; i < end_loop_index; i++) {
sum += i;
}
return(sum);
}
LLVm byte-code disassembly:
; Function Attrs: nounwind readnone
define i32 @simple_loop(i32 %end_loop_index) #1 {
entry:
%cmp4 = icmp sgt i32 %end_loop_index, 0
br i1 %cmp4, label %for.cond.for...
2014 Oct 29
2
[LLVMdev] Virtual register def doesn't dominate all uses
...with implemented operations as well.
>>
>> What did I do wrong? Missing implementation for some operations? What did I miss to implement?
>>
>> Thanks in advance,
>> Boris
>>
>> ----8<----
>>
>> C source-code:
>> int simple_loop(int end_loop_index)
>> {
>> int sum = 0;
>> for(int i = 0; i < end_loop_index; i++) {
>> sum += i;
>> }
>> return(sum);
>> }
>>
>>
>> LLVm byte-code disassembly:
>> ; Function Attrs: nounwind readnone
>> define i32 @simple_loop(i32 %end_lo...
2014 Oct 31
2
[LLVMdev] Virtual register def doesn't dominate all uses
...I do wrong? Missing implementation for some operations? What did I miss to implement?
>>>>
>>>> Thanks in advance,
>>>> Boris
>>>>
>>>> ----8<----
>>>>
>>>> C source-code:
>>>> int simple_loop(int end_loop_index)
>>>> {
>>>> int sum = 0;
>>>> for(int i = 0; i < end_loop_index; i++) {
>>>> sum += i;
>>>> }
>>>> return(sum);
>>>> }
>>>>
>>>>
>>>> LLVm byte-code disassembly:
>>>...
2014 Nov 01
2
[LLVMdev] Virtual register def doesn't dominate all uses
...d I miss to implement?
>>>>>>
>>>>>> Thanks in advance,
>>>>>> Boris
>>>>>>
>>>>>> ----8<----
>>>>>>
>>>>>> C source-code:
>>>>>> int simple_loop(int end_loop_index)
>>>>>> {
>>>>>> int sum = 0;
>>>>>> for(int i = 0; i < end_loop_index; i++) {
>>>>>> sum += i;
>>>>>> }
>>>>>> return(sum);
>>>>>> }
>>>>>>
>>&g...
2014 Dec 05
2
[LLVMdev] illegal code generated for special architecture
...oad and store and address-registers in my target instruction patterns:
eg (store (add (load AddressRegs:$a), DataRegs:$b), AddressRegs:$dst)
This works quite well, but if I access an array on the stack (LLVM generates FrameIndex to access it):
int buffer[BUFFER_SIZE];
for(int i = 0; i < end_loop_index; i++) {
buffer[i] = i;
}
then LLVM generates the target instruction "ADD D1, A1, D0" which is an illegal instruction - all operands have to be data-registers Dx. I've checked more than once, that address-registers are not in the set of data-registers. The generated instruction...