Displaying 10 results from an estimated 10 matches for "encsize".
2015 Feb 06
2
[PATCH 1/3] nv50/ir: Add support for MAD 4-byte opcode
...rc/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
index 2077388..23e4bab 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -941,7 +941,10 @@ CodeEmitterNV50::emitFMAD(const Instruction *i)
if (i->encSize == 4) {
emitForm_MUL(i);
- assert(!neg_mul && !neg_add);
+ code[0] |= neg_mul << 15;
+ code[0] |= neg_add << 22;
+ if (i->saturate)
+ code[0] |= 1 << 8;
} else {
code[1] = neg_mul << 26;
code[1] |= neg_add <...
2015 Jan 11
1
[PATCH 1/3] nv50/ir: Add support for MAD short+IMM notation
...FILE_IMMEDIATE) {
>> + code[1] = 0;
>> + emitForm_IMM(i);
>> + code[0] |= neg_mul << 15;
>> + code[0] |= neg_add << 22;
>> + if (i->saturate)
>> + code[0] |= 1 << 8;
>> + } else
>> if (i->encSize == 4) {
>> emitForm_MUL(i);
>> - assert(!neg_mul && !neg_add);
>> + code[0] |= neg_mul << 15;
>> + code[0] |= neg_add << 22;
>> + if (i->saturate)
>> + code[0] |= 1 << 8;
>> } else {
>...
2015 Jan 11
6
[PATCH 1/3] nv50/ir: Add support for MAD short+IMM notation
...tion *i)
code[0] = 0xe0000000;
+ if (i->src(1).getFile() == FILE_IMMEDIATE) {
+ code[1] = 0;
+ emitForm_IMM(i);
+ code[0] |= neg_mul << 15;
+ code[0] |= neg_add << 22;
+ if (i->saturate)
+ code[0] |= 1 << 8;
+ } else
if (i->encSize == 4) {
emitForm_MUL(i);
- assert(!neg_mul && !neg_add);
+ code[0] |= neg_mul << 15;
+ code[0] |= neg_add << 22;
+ if (i->saturate)
+ code[0] |= 1 << 8;
} else {
code[1] = neg_mul << 26;
code[1] |= neg_add <...
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...+
emitForm_MAD(i);
}
@@ -963,6 +968,26 @@ CodeEmitterNV50::emitFMAD(const Instruction *i)
}
void
+CodeEmitterNV50::emitDMAD(const Instruction *i)
+{
+ const int neg_mul = i->src(0).mod.neg() ^ i->src(1).mod.neg();
+ const int neg_add = i->src(2).mod.neg();
+
+ assert(i->encSize == 8);
+ assert(!i->saturate);
+
+ code[1] = 0x40000000;
+ code[0] = 0xe0000000;
+
+ code[1] |= neg_mul << 26;
+ code[1] |= neg_add << 27;
+
+ roundMode_MAD(i);
+
+ emitForm_MAD(i);
+}
+
+void
CodeEmitterNV50::emitFADD(const Instruction *i)
{
const int neg0 = i-&g...
2015 Jan 23
3
[PATCH 1/2] nv50/ir: Add support for MAD short+IMM notation
...tion *i)
code[0] = 0xe0000000;
+ if (i->src(1).getFile() == FILE_IMMEDIATE) {
+ code[1] = 0;
+ emitForm_IMM(i);
+ code[0] |= neg_mul << 15;
+ code[0] |= neg_add << 22;
+ if (i->saturate)
+ code[0] |= 1 << 8;
+ } else
if (i->encSize == 4) {
emitForm_MUL(i);
- assert(!neg_mul && !neg_add);
+ code[0] |= neg_mul << 15;
+ code[0] |= neg_add << 22;
+ if (i->saturate)
+ code[0] |= 1 << 8;
} else {
code[1] = neg_mul << 26;
code[1] |= neg_add <...
2015 Jan 04
0
[PATCH] nv50/ir: Add sat modifier for mul
...v50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -1059,16 +1059,22 @@ CodeEmitterNV50::emitFMUL(const Instruction *i)
emitForm_IMM(i);
if (neg)
code[0] |= 0x8000;
+ if (i->saturate)
+ code[0] |= 1 << 8;
} else
if (i->encSize == 8) {
code[1] = i->rnd == ROUND_Z ? 0x0000c000 : 0;
if (neg)
code[1] |= 0x08000000;
+ if (i->saturate)
+ code[1] |= 1 << 20;
emitForm_MAD(i);
} else {
emitForm_MUL(i);
if (neg)
code[0] |= 0x8000;
+ if (i->...
2015 Jan 11
0
[PATCH 1/3] nv50/ir: Add support for MAD short+IMM notation
...if (i->src(1).getFile() == FILE_IMMEDIATE) {
> + code[1] = 0;
> + emitForm_IMM(i);
> + code[0] |= neg_mul << 15;
> + code[0] |= neg_add << 22;
> + if (i->saturate)
> + code[0] |= 1 << 8;
> + } else
> if (i->encSize == 4) {
> emitForm_MUL(i);
> - assert(!neg_mul && !neg_add);
> + code[0] |= neg_mul << 15;
> + code[0] |= neg_add << 22;
> + if (i->saturate)
> + code[0] |= 1 << 8;
> } else {
> code[1] = neg_mul <...
2014 May 30
4
[Bug 79462] New: [NVC0/Codegen] Shader compilation falis in spill logic
...s
case, apparently a null value??
(gdb) p *defi
$4 = {_vptr.Instruction = 0x86e570, next = 0x0, prev = 0x0, id = -1, serial =
27, op = nv50_ir::OP_SPLIT,
dType = nv50_ir::TYPE_B128, sType = nv50_ir::TYPE_B128, cc = nv50_ir::CC_TR,
rnd = nv50_ir::ROUND_N,
cache = nv50_ir::CACHE_CA, subOp = 0, encSize = 0, saturate = 0, join = 0,
fixed = 0, terminator = 0,
ftz = 0, dnz = 0, ipa = 0, lanes = 15, perPatch = 0, exit = 0, mask = 0,
postFactor = 0 '\000',
predSrc = -1 '\377', flagsDef = -1 '\377', flagsSrc = -1 '\377', sched = 0,
bb = 0x0,
defs = std::deque wi...
2015 Jan 13
3
nv50/ir: Implement short notation for MAD V2
V2: clarify code, commit msgs, add comments. Drop code to was supposed to
make register assignment prefer SDST == SRC2 (patch 2) for now, because it
didn't quite do what I intended.
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
...+ emitForm_A(i, HEX64(50000000, 00000001));
+ roundMode_A(i);
+
+ if (neg)
+ code[0] |= 1 << 9;
+
+ assert(!i->saturate);
+ assert(!i->ftz);
+ assert(!i->dnz);
+ assert(!i->postFactor);
+}
+
+void
CodeEmitterNVC0::emitUMUL(const Instruction *i)
{
if (i->encSize == 8) {
@@ -619,6 +658,19 @@ CodeEmitterNVC0::emitFADD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDADD(const Instruction *i)
+{
+ assert(i->encSize == 8);
+ emitForm_A(i, HEX64(48000000, 00000001));
+ roundMode_A(i);
+ assert(!i->saturate);
+ assert(!i->ftz);
+ emit...