Displaying 4 results from an estimated 4 matches for "encodefixedtyp".
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encodefixedtype
2016 Sep 18
4
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...lt;<error:unhandled vector type width in intrinsic!>>
This error comes from this file
https://github.com/llvm-mirror/llvm/blob/master/utils/TableGen/IntrinsicEmitter.cpp,
comes from the fact there is no IIT_V128 (nor IIT_V256), and they is a
switch case using them in method static void EncodeFixedType(Record *R,
std::vector<unsigned char> &ArgCodes, std::vector<unsigned char> &Sig).
Is there any reason these enum IIT_Info ( IIT_V128, IIT_V256) are not
added in file /IntrinsicEmitter.cpp?
Thank you,
Alex
On Tue, Sep 13, 2016 at 1:47 AM, Matthias Braun <mbraun...
2017 Jul 28
2
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...This error comes from this file
>>> https://github.com/llvm-mirror/llvm/blob/master/utils/TableGen/IntrinsicEmitter.cpp,
>>> comes
>>> from the fact there is no IIT_V128 (nor IIT_V256), and they is a
>>> switch case using them in
>>> method static void EncodeFixedType(Record *R, std::vector<unsigned
>>> char> &ArgCodes,
>>> std::vector<unsigned char> &Sig).
>>>
>>> Is there any reason these enum IIT_Info ( IIT_V128, IIT_V256) are
>>> not added in file
>>> /IntrinsicEmitter.cpp?
>...
2017 Jul 28
0
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...idth in intrinsic!>>
>> This error comes from this file
>> https://github.com/llvm-mirror/llvm/blob/master/utils/TableGen/IntrinsicEmitter.cpp, comes
>> from the fact there is no IIT_V128 (nor IIT_V256), and they is a switch case using them in
>> method static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes,
>> std::vector<unsigned char> &Sig).
>>
>> Is there any reason these enum IIT_Info ( IIT_V128, IIT_V256) are not added in file
>> /IntrinsicEmitter.cpp?
>>
>> Thank you,
>> Alex...
2016 Sep 08
2
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
Hello.
In my TableGen back end description I need to use more than 32 (e.g., 128, 1024, etc)
subregisters per register for my research SIMD processor. I have used so far with success
32 subregisters.
However, when using 128 subregisters when I now give the command:
llvm-tblgen -gen-register-info Connex.td
I get an error message "error:Ran out of lanemask bits to