search for: enablepostrascheduler

...- XCore As part of this, I'd fix tests that fail due to instruction re-orderings, but, I *wouldn't* try to do performance testing of any sort. The targets from the above list that still use the old code which surprise me are ARM and PPC. However, both also usually seem to return true from enablePostRAScheduler -- maybe they really just want to avoid doing machine scheduling both pre-RA and post-RA, and the fact that it also causes the old selectiondag scheduler to get used is an unintended consequence? (And thus, would actually want enableMachineScheduler() -> false, but with Sched::Source as the sele...

...ng &TT, const std::string &CPU, // Parse features string. ParseSubtargetFeatures(CPUName, FS); + PreviousInMips16Mode = InMips16Mode; + // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); @@ -72,3 +92,45 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass); return OptLevel >= CodeGenOpt::Aggressive; } +void MipsSubtarget::resetSubtarget(MachineFunction *MF) { + bool ChangeToMips16 = false, ChangeToNoMips16 = false; + DEBUG(dbgs...

...vm::DenseMapInfo<unsigned int> >&, bool, bool, bool)in libLLVMSelectionDAG.a(InstrEmitter.cpp.o) llvm::DAGTypeLegalizer::ExpandRes_BIT_CONVERT(llvm::SDNode*, llvm::SDValue&, llvm::SDValue&)in libLLVMSelectionDAG.a(LegalizeTypesGeneric.cpp.o) "llvm::TargetSubtarget::enablePostRAScheduler(llvm::CodeGenOpt::Level, llvm::TargetSubtarget::AntiDepBreakMode&, llvm::SmallVectorImpl<llvm::TargetRegisterClass*>&) const", referenced from: vtable for llvm::EBCSubtargetin libLLVMEBCCodeGen.a(EBCTargetMachine.cpp.o) vtable for llvm::EBCSubtargetin libLLVMEBCCodeGe...

On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote: > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if the > attributes changed). Do you have another solution in mind ? I don't really understand this. TargetMachine and TTI may be quite expensive to initialize. Doing so for

...vm::DenseMapInfo<unsigned int> >&, bool, bool, bool)in libLLVMSelectionDAG.a(InstrEmitter.cpp.o) llvm::DAGTypeLegalizer::ExpandRes_BIT_CONVERT(llvm::SDNode*, llvm::SDValue&, llvm::SDValue&)in libLLVMSelectionDAG.a(LegalizeTypesGeneric.cpp.o) "llvm::TargetSubtarget::enablePostRAScheduler(llvm::CodeGenOpt::Level, llvm::TargetSubtarget::AntiDepBreakMode&, llvm::SmallVectorImpl<llvm::TargetRegisterClass*>&) const", referenced from: vtable for llvm::EBCSubtargetin libLLVMEBCCodeGen.a(EBCTargetMachine.cpp.o) vtable for llvm::EBCSubtargetin libLLVMEBCCodeGe...

...s sincos() routine in its >> /// compiler runtime or math libraries. >> bool hasSinCos() const; >> >> + /// Enable the MachineScheduler pass for all X86 subtargets. >> + bool enableMachineScheduler() const LLVM_OVERRIDE { return true; } >> + >> /// enablePostRAScheduler - run for Atom optimization. >> bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, >> TargetSubtargetInfo::AntiDepBreakMode& Mode, >> >> Modified: llvm/trunk/test/CodeGen/X86/2006-05-02-InstrSched1.ll >> URL: http://llvm.org/view...

...;, "SplitEdges"}, {"_ZL15defaultRegAlloc", "defaultRegAlloc"}, {"_ZL8RegAlloc", "RegAlloc"}, {"_ZL10Aggressive", "Aggressive"}, {"_ZL15DisablePeephole", "DisablePeephole"}, {"_ZL21EnablePostRAScheduler", "EnablePostRAScheduler"}, {"_ZL21EnableAntiDepBreaking", "EnableAntiDepBreaking"}, {"_ZL8DebugDiv", "DebugDiv"}, {"_ZL8DebugMod", "DebugMod"}, {"_ZL13PreSplitLimit", "PreSplitLimit"}...