Displaying 6 results from an estimated 6 matches for "enablejoining".
2007 Apr 14
2
[LLVMdev] command line option
...ed in
LiveIntervalAnalysis, but I want my option to be visible among many
passes, and not only one. I browsed the documentation, but I did not find
the info I was looking for. Could any of you tell me a little about it?
I mean, do I have to write something like:
static cl::opt<bool>
EnableJoining("join-liveintervals",
cl::desc("Join compatible live intervals"),
cl::init(true));
in some .h, and then include it in every pass that would read
EnableJoining? Is there a standard way of doing this?
best,
Fernando
2007 Apr 14
0
[LLVMdev] command line option
On Sat, 14 Apr 2007, Fernando Magno Quintao Pereira wrote:
> the info I was looking for. Could any of you tell me a little about it?
> I mean, do I have to write something like:
>
> static cl::opt<bool>
> EnableJoining("join-liveintervals",
> cl::desc("Join compatible live intervals"),
> cl::init(true));
>
> in some .h, and then include it in every pass that would read
> EnableJoining? Is there a standard way of doing this?
You want to use "...
2015 Mar 18
2
[LLVMdev] missing register spills?
Hi folks,
I'm running into this weird issue where the register spills appear to be missing for an "if" block for some reason. For example, the original if/else blocks:
---
if reg0
// storeRegToStackSlot for reg1
// do something
- missing a load for reg1?
else
// storeRegToStackSlot for reg1
// do something
// loadRegFromStackSlot for reg1
end
----
I tried looking in the LLVM
2017 Jun 21
6
RFC: Cleaning up the Itanium demangler
...egsE", "(anonymous namespace)::NumRecentlyUsedRegs"},
{"_ZL14ShrinkWrapping", "ShrinkWrapping"},
{"_ZL14ShrinkWrapFunc", "ShrinkWrapFunc"},
{"_ZL19ShrinkWrapDebugging", "ShrinkWrapDebugging"},
{"_ZL13EnableJoining", "EnableJoining"},
{"_ZL21DisableCrossClassJoin", "DisableCrossClassJoin"},
{"_ZL19DisablePhysicalJoin", "DisablePhysicalJoin"},
{"_ZL16VerifyCoalescing", "VerifyCoalescing"},
{"_ZL10spillerOpt"...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2