Displaying 6 results from an estimated 6 matches for "enableinterleavedaccessvector".
2016 May 26
2
enabling interleaved access loop vectorization
Is there a compile-time and/or potential runtime cost that makes
enableInterleavedAccessVectorization() default to 'false'?
I notice that this is set to true for ARM, AArch64, and PPC.
In particular, I'm wondering if there's a reason it's not enabled for x86
in relation to PR27881:
https://llvm.org/bugs/show_bug.cgi?id=27881
-------------- next part --------------
An HT...
2016 May 26
0
enabling interleaved access loop vectorization
On 26 May 2016 at 19:12, Sanjay Patel via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Is there a compile-time and/or potential runtime cost that makes
> enableInterleavedAccessVectorization() default to 'false'?
>
> I notice that this is set to true for ARM, AArch64, and PPC.
>
> In particular, I'm wondering if there's a reason it's not enabled for x86 in
> relation to PR27881:
> https://llvm.org/bugs/show_bug.cgi?id=27881
Hi Sanjay,
The...
2016 May 26
2
enabling interleaved access loop vectorization
...sts.llvm.org>
>Subject: Re: [llvm-dev] enabling interleaved access loop vectorization
>
>On 26 May 2016 at 19:12, Sanjay Patel via llvm-dev <llvm-
>dev at lists.llvm.org> wrote:
>> Is there a compile-time and/or potential runtime cost that makes
>> enableInterleavedAccessVectorization() default to 'false'?
>>
>> I notice that this is set to true for ARM, AArch64, and PPC.
>>
>> In particular, I'm wondering if there's a reason it's not enabled for
>> x86 in relation to PR27881:
>> https://llvm.org/bu...
2016 Aug 05
3
enabling interleaved access loop vectorization
...[llvm-dev] enabling interleaved access loop vectorization
>
>On 26 May 2016 at 19:12, Sanjay Patel via llvm-dev <llvm-
>dev at lists.llvm.org<mailto:dev at lists.llvm.org>> wrote:
>> Is there a compile-time and/or potential runtime cost that makes
>> enableInterleavedAccessVectorization() default to 'false'?
>>
>> I notice that this is set to true for ARM, AArch64, and PPC.
>>
>> In particular, I'm wondering if there's a reason it's not enabled for
>> x86 in relation to PR27881:
>> https://llvm.org/bu...
2016 Aug 05
2
enabling interleaved access loop vectorization
...ubject: Re: [llvm-dev] enabling interleaved access loop vectorization
> >
> >On 26 May 2016 at 19:12, Sanjay Patel via llvm-dev <llvm-
> >dev at lists.llvm.org> wrote:
> >> Is there a compile-time and/or potential runtime cost that makes
> >> enableInterleavedAccessVectorization() default to 'false'?
> >>
> >> I notice that this is set to true for ARM, AArch64, and PPC.
> >>
> >> In particular, I'm wondering if there's a reason it's not enabled for
> >> x86 in relation to PR27881:
>...
2016 Sep 01
2
enabling interleaved access loop vectorization
So turns out it is a full reproducer after all (choosing to vectorize on AVX), good.
> The details are in PR29025.
Interesting. (So we should carefully insert unconditional branches inside shuffle sequences, eh? ;-)
> But if we modify the program by adding "*out++ = 0" right after "*out++ = q;" (thus eliminating the pesky <12 x i8>), we get:
Indeed such