search for: emm

Hi all, We followed some books and sample codes and did some EMM estimation, only to find it won't be able to generate forecast. This is because in the stochastic volatility models we are estimating, the volatilities are latent variables, and we want to forecast 1-step ahead or h-step ahead volatilities. So it is nice to have the system estimated, but we c...

I just uploaded two packages to CRAN. shapefiles_0.1.tar.gz - functions to read and write ESRI shapefiles (including dbfs) emme2_0.1.tar.gz - functions to read binary data from an EMME/2 databank data (EMME/2 is a transportation modeling program) Please let me know if you find any bugs or have some suggestions. Thanks. Regards, Benjamin Stabler Transportation Planning Analysis Unit Oregon Department of Transportation 55...

Instead of emm-dashes I get struck-out text surrounded with single hyphens. RedCloth 3.0.4: >> d = RedCloth.new "-- hyphens to the left of me, hyphens to the right, all should be emm dashes --" => "-- hyphens to the left of me, hyphens to the right, all should be emm dashes --" &g...

...t;> make up for the added register pressure. So I'm not keen to implement >> this option, unless anyone sees some advantages that I missed? > It's my understanding that SSE is by far superior to MMX for a number of reasons, not the least of which is the need to use the expensive EMMS instruction. Instead of guessing about the performance impact, I would encourage you to test this out. I'm already explicitly using EMMS, where necessary. Basically when avoiding x87 (and avoiding library calls which may use x87), it's not needed. So there's no performance drawback f...

...t;EPT.AV120", stdev="EPT.SD120")) mrets <- merge(mrets, EVA.SR=apply(mrets, 1, MyFunc, ret="EVA.AV120", stdev="EVA.SD120")) mrets <- merge(mrets, EMT.SR=apply(mrets, 1, MyFunc, ret="EMT.AV120", stdev="EMT.SD120")) mrets <- merge(mrets, EMM.SR=apply(mrets, 1, MyFunc, ret="EMM.AV120", stdev="EMM.SD120")) mrets <- merge(mrets, EMV.SR=apply(mrets, 1, MyFunc, ret="EMV.AV120", stdev="EMV.SD120")) mrets <- merge(mrets, ETM.SR=apply(mrets, 1, MyFunc, ret="ETM.AV120", stdev="ETM.SD1...

On Sep 7, 2010, at 7:45 AM, Nicolas Capens wrote: > Hi all, > > I've tested a recent revision and noticed that using 64-bit vectors became very slow. It looks like they are expanded to non-MMX instructions to avoid breaking code which does not clear the MMX state using emms? > > For my project I'm already manually inserting emms instructions in the right places, so I'd really like 64-bit vector operations to be lowered to MMX instructions for best performance. So is there some way to get that behavior back? I tried making IsVerbotenVectorType return f...

...that don't work in our own words. Lets do this for the llvm 2.3 release notes though, after Monday. > The miscompilation of code containing both MMX vectors and long double > may be worth a mention, but it probably isn't going to bite very many > people. (llvm does not insert EMMS everywhere it needs to, or from a > different viewpoint, uses MMX when the user didn't tell it to.) AFAIK, many commonly used GCC versions don't do this either. If that's the case, I don't think it's worth mentioning, because most people will be concerned with "ll...

...n't > make up for the added register pressure. So I'm not keen to implement > this option, unless anyone sees some advantages that I missed? It's my understanding that SSE is by far superior to MMX for a number of reasons, not the least of which is the need to use the expensive EMMS instruction. Instead of guessing about the performance impact, I would encourage you to test this out. > 2) Since I use MMX intrinsics, I take care of inserting the appropriate > EMMS instructions myself as well. So it's absolutely fine to have LLVM > lower 64-bit operations into M...

...unity for using v8i16 to perform two v4i16 operations simultaneously so that won't make up for the added register pressure. So I'm not keen to implement this option, unless anyone sees some advantages that I missed? 2) Since I use MMX intrinsics, I take care of inserting the appropriate EMMS instructions myself as well. So it's absolutely fine to have LLVM lower 64-bit operations into MMX instructions (the way it used to be in LLVM 2.8). Would it be straightforward to re-enable this? I noticed that revision 115243 removes the MMX lowering rules, but I don't know if the res...

...ake up for the added register pressure. So I'm not keen to implement >>> this option, unless anyone sees some advantages that I missed? >> It's my understanding that SSE is by far superior to MMX for a number of reasons, not the least of which is the need to use the expensive EMMS instruction. Instead of guessing about the performance impact, I would encourage you to test this out. > I'm already explicitly using EMMS, where necessary. Basically when avoiding x87 (and avoiding library calls which may use x87), it's not needed. So there's no performance drawbac...

...such code is being used in a performance critical location now, it really shouldn't be using MMX still, so I don't think this is a seriosu issue. For _mm_empty, I think the best thing to do is to follow what GCC did, and make it a no-op only if MMX is disabled, and have it continue to emit EMMS otherwise -- even though that is usually a waste. > 1. The calling convention problem; your description covers this. > > Well, I covered it...but I didn't come to an actual conclusion there. :) If we add an explicit opt-in, I don’t see any problem with emulation (even > on no...

...t be optimized like other vector >> operations. I could use SSE operations, but they would increase SSE register >> pressure while MMX registers are left unused. >> >> So ideally I would like to inform LLVM that selecting MMX instructions is >> fine. I'm inserting emms instructions in the right spots myself. > > I think the direction going forward we're going to prefer is that > 64-bit vectors get widened to 128-bit vectors, which might not be > quite ideal in some situations, but will avoid situations where MMX > instructions are incorrectly...

...words. Lets do this for the llvm > 2.3 release notes though, after Monday. ok. >> The miscompilation of code containing both MMX vectors and long >> double >> may be worth a mention, but it probably isn't going to bite very many >> people. (llvm does not insert EMMS everywhere it needs to, or from a >> different viewpoint, uses MMX when the user didn't tell it to.) > > AFAIK, many commonly used GCC versions don't do this either. If > that's the case, I don't think it's worth mentioning, because most > people will be conc...

Hi all, I'm trying to compile asterisk on the mainframe (s390 / s390x) and I am running into issues. I was wondering if somebody could give a hand? I'm thinking that I should be able to do this. I have noticed that Debian even has binary RPM's out for Asterisk now. I'm trying to do this on SuSE SLES8 (with the 2.4 kernel). What I see is, an issue that arch=s390 isn't

...y! Instead, every x87 instruction will simply result in a NaN value. Even more unfortunately than all that, it is currently impossible to correctly use _mm_empty() to resolve the problem, because the compiler has no restrictions against placing x87 FPU operations between an MMX instruction and the EMMS instruction. Of course, I didn't discover any of this -- it was already well-known...just not to me. But let's actually fix it. *Existing bugs*: llvm.org/PR35982 <https://bugs.llvm.org/show_bug.cgi?id=35982> -- POSTRAScheduler disarrange emms and mmx instruction llvm.org/PR41029 &l...

...be >> messing it up. > > I would call that "user error"; basically, using MMX instructions > messes up the FP stack, and we assume the user is smart enough to make > sure the two don't mix. More specifically, if you use MMX/3dNow intrinsics, you have to call "emms" at ABI boundaries. -Chris

...description would be a good idea, that's pure propaganda: sometimes it's true and sometimes it isn't. The miscompilation of code containing both MMX vectors and long double may be worth a mention, but it probably isn't going to bite very many people. (llvm does not insert EMMS everywhere it needs to, or from a different viewpoint, uses MMX when the user didn't tell it to.) Giving me credit for darwin x86-64 EH is an overstatement, I just made minor mods to existing EH code (Anton's I think). Looks good overall.

Hi All, The first draft of the llvm 2.2 release notes are now available: http://llvm.org/docs/ReleaseNotes.html The release is scheduled for Monday, so please take a look at them and send me your feedback, or (better yet) just commit fixes directly to the document in llvm/docs/ReleaseNotes.html. In addition to editing improvements I'm particularly interested in adding missing things

On Aug 31, 2010, at 10:19 PM, Chris Lattner wrote: > > Hi Argiris, > > The real problem here is that the X86 backend is turning datatypes like <1 x i64> into MMX operations, but doesn't do so in a safe way (it's not inserting the requisite EMMS instructions). After discussing this with Dale and Bill, the right fix is to stop mapping generic vectors onto MMX operations. This will define away the existing -disable-mmx flag and make stuff like this impossible. > > However, this isn't going to happen in the next couple days, cer...

...lem ? > I also attached 't.cpp' which approximates the source that the .ll files came from. Hi Argiris, The real problem here is that the X86 backend is turning datatypes like <1 x i64> into MMX operations, but doesn't do so in a safe way (it's not inserting the requisite EMMS instructions). After discussing this with Dale and Bill, the right fix is to stop mapping generic vectors onto MMX operations. This will define away the existing -disable-mmx flag and make stuff like this impossible. However, this isn't going to happen in the next couple days, certainly not...