search for: emitters

On Fri, Feb 05, 2016 at 04:58:45PM -0800, Mehdi Amini wrote: > > > On Feb 5, 2016, at 3:17 PM, Peter Collingbourne via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > Hi all, > > > > We have profiled [1] the memory usage in LLVM when LTO'ing Chromium, and > > we've found that one of the top consumers of memory is the DWARF emitter in

...r the register allocation. Thanks for the reply! -Jafar J From: Jim Grosbach Sent: Thursday, May 30, 2013 7:55 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re: [LLVMdev] Activating MIPS Code Emitter. What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter...

Hi there, I think I've found a bug in the x86 JIT. I get an assertion failure when using thread-local variables and the fast emitter. It only happens with the JIT, the fast emiiter and thread-locals. (The IR passes the verifier) Here's the failure: X86CodeEmitter.cpp:516: void<unnamed>::Emitter::emitInstruction(const llvm::MachineInstr&, const llvm::TargetInstrDesc*):

...gt;>> From: Jim Grosbach >>> Sent: Thursday, May 30, 2013 7:55 PM >>> To: Jafar J >>> Cc: llvmdev at cs.uiuc.edu ; Mailing List >>> Subject: Re: [LLVMdev] Activating MIPS Code Emitter. >>> >>> What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. >>> >>> -Jim >>> >>> On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: >>> >>>> Hello, >>>> Is it possible to activate the MIPS code emitter during P...

...e available after the register allocation. Thanks for the reply! -Jafar J From: Jim Grosbach Sent: Thursday, May 30, 2013 7:55 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re: [LLVMdev] Activating MIPS Code Emitter. What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h...

On Fri, Feb 5, 2016 at 5:51 PM Mehdi Amini via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > On Feb 5, 2016, at 5:40 PM, Peter Collingbourne <peter at pcc.me.uk> wrote: > > > > On Fri, Feb 05, 2016 at 04:58:45PM -0800, Mehdi Amini wrote: > >> > >>> On Feb 5, 2016, at 3:17 PM, Peter Collingbourne via llvm-dev < > llvm-dev at

...t;> -Jafar J >> >> From: Jim Grosbach >> Sent: Thursday, May 30, 2013 7:55 PM >> To: Jafar J >> Cc: llvmdev at cs.uiuc.edu ; Mailing List >> Subject: Re: [LLVMdev] Activating MIPS Code Emitter. >> >> What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. >> >> -Jim >> >> On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: >> >>> Hello, >>> Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried in...

Hi all, when trying to build LLVM+Clang (r180247) on a BlueGene/Q, I get the following error message (multiple times): llvm[3]: Building PPC.td code emitter with tblgen llvm-tblgen: Unknown command line argument '-gen-emitter'. Try: '/homea/jjsc13/jjsc1301/.pool/.build/llvm_r180241/Release+Asserts/bin/llvm-tblgen -help' llvm-tblgen: Did you mean '-mc-emitter'? Has

...which will be available after the register allocation. Thanks for the reply! -Jafar J From: Jim Grosbach Sent: Thursday, May 30, 2013 7:55 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re: [LLVMdev] Activating MIPS Code Emitter. What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to Post...

...> Thanks for the reply! > > -Jafar J > > From: Jim Grosbach > Sent: Thursday, May 30, 2013 7:55 PM > To: Jafar J > Cc: llvmdev at cs.uiuc.edu ; Mailing List > Subject: Re: [LLVMdev] Activating MIPS Code Emitter. > > What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. > > -Jim > > On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: > >> Hello, >> >> Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both Mip...

X86 JIT does not yet support TLS. Evan On Jun 12, 2009, at 2:48 AM, Mark Shannon wrote: > Hi there, > > I think I've found a bug in the x86 JIT. I get an assertion failure > when > using thread-local variables and the fast emitter. > It only happens with the JIT, the fast emiiter and thread-locals. > (The IR passes the verifier) > > Here's the failure: >

Hi all, We have profiled [1] the memory usage in LLVM when LTO'ing Chromium, and we've found that one of the top consumers of memory is the DWARF emitter in lib/CodeGen/AsmPrinter/Dwarf*. I've been reading the DWARF emitter code and I have a few ideas in mind for how to reduce its memory consumption. One idea I've had is to restructure the emitter so that (for the most part) it

Evan, Any plans to add it any time soon? It would be really appreciated. Evan Cheng wrote: > X86 JIT does not yet support TLS. > > Evan > On Jun 12, 2009, at 2:48 AM, Mark Shannon wrote: > >> Hi there, >> >> I think I've found a bug in the x86 JIT. I get an assertion failure >> when >> using thread-local variables and the fast emitter.

...should be used for functions only). The assert() is triggered because the global variable is dumped to the header of the free blocks list (provided that ThisAllocated becomes 1). My proposed patch: http://web.ist.utl.pt/nuno.lopes/llvm_jit_global_emitter.txt (similar to what other JIT variable emitters do). Please comment. Thanks, Nuno

Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet

What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hello, > > Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h...

No plans. I recommend you hack on it. :-) Sorry, all features are done on demand. Evan On Jun 12, 2009, at 1:08 PM, Mark Shannon wrote: > Evan, > > Any plans to add it any time soon? > It would be really appreciated. > > Evan Cheng wrote: >> X86 JIT does not yet support TLS. >> >> Evan >> On Jun 12, 2009, at 2:48 AM, Mark Shannon wrote: >>

On Fri, Feb 5, 2016 at 5:56 PM, Mehdi Amini via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > On Feb 5, 2016, at 5:53 PM, Eric Christopher <echristo at gmail.com> wrote: > > > > On Fri, Feb 5, 2016 at 5:51 PM Mehdi Amini via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> > On Feb 5, 2016, at 5:40 PM, Peter Collingbourne

...assert() > is triggered because the global variable is dumped to the header of > the free > blocks list (provided that ThisAllocated becomes 1). > > My proposed patch: > http://web.ist.utl.pt/nuno.lopes/llvm_jit_global_emitter.txt > (similar to > what other JIT variable emitters do). > > Please comment. > > Thanks, > Nuno > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...of field declared in the instruction with the name of the operand in order to determine which operand of the MI to use . See CodeEmitterGen.cpp:170 and neighborhood. Unfortunately there are naming discrepancies between the instruction format fields and the operand names in all existing code emitters that use TableGen, which would require some significant renaming cleanup. Thoughts on binding operand names to instruction field names for the code emitter? -- Christopher Lamb -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piperm...