search for: emitmachinenode

...> each desired set of call-clobbered registers. The problem is the large number of call-like instructions. We would need copies of CALL*, TCRETURN*, and TAILJMP* for each calling convention. I was hoping we could avoid that, and even get rid of the WINCALL instructions. What if InstrEmitter::EmitMachineNode called a target hook to add call-clobbered registers when II.isCall()? We would need some way of communicating the calling convention to the target hook. An immediate operand could work. /jakob

Hi all, I need to figure out why InstrEmitter::EmitMachineNode assumes that when the number of outputs of a MachineSDNode is greater than the number of defs in the corresponding MCInstrDesc, the outputs in the difference will be placed into physical registers as opposed to virtual registers. The specific line in question is: bool HasPhysRegOuts = NumResul...

On Oct 19, 2010, at 8:00 PM, Jakob Stoklund Olesen wrote: > > > One problem is that calling conventions are handled while building the selection DAG, and the DAG doesn't really know to represent clobbered registers. > > Perhaps X86TargetLowering::LowerCall() could decorate the X86ISD::CALL node with the calling convention somehow? > > Dan, do you have any thoughts on

...nd write 0 to higher part. Finally, these parts are glued together using ISD::BUILD_PAIR. However, when I try to insert such nodes into the DAG within TriCoreTargetLowering, I run into an assertion: llc: /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion `NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && "#operands for dag node doesn't match .td file!"' failed. C...

...; the value is going to end up and that’s only achievable in a physical > register. > > Cheers, > -Quentin > > On Nov 18, 2019, at 6:21 PM, Thomas Lively via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I need to figure out why InstrEmitter::EmitMachineNode assumes that when > the number of outputs of a MachineSDNode is greater than the number of defs > in the corresponding MCInstrDesc, the outputs in the difference will be > placed into physical registers as opposed to virtual registers. > > The specific line in question is: > b...

...ally, these parts are glued together using ISD::BUILD_PAIR. > However, when I try to insert such nodes into the DAG within > TriCoreTargetLowering, I run into an assertion: > > llc: > /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: > void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, > llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion > `NumMIOperands >= II.getNumOperands() && NumMIOperands <= > II.getNumOperands()+II.getNumImplicitDefs() && "#operands for dag node > doesn't match .td file!&q...

...lued together using ISD::BUILD_PAIR. >> However, when I try to insert such nodes into the DAG within >> TriCoreTargetLowering, I run into an assertion: >> >> llc: >> /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: >> void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, >> llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion >> `NumMIOperands >= II.getNumOperands() && NumMIOperands <= >> II.getNumOperands()+II.getNumImplicitDefs() && "#operands for dag node >> doesn't m...

...d CFG by the scheduler. The high level ScheduleDAGSDNodes::EmitSchedule does this: for (unsigned i = 0, e = Sequence.size(); i != e; i++) { [...] Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap); [...] } TheInstrEmitter::EmitMachineNode does this: if (II.usesCustomInsertionHook()) { // Insert this instruction into the basic block using a target // specific inserter which may returns a new basic block. bool AtEnd = InsertPos == MBB->end(); MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB...

...ly achievable in a physical >> register. >> >> Cheers, >> -Quentin >> >> On Nov 18, 2019, at 6:21 PM, Thomas Lively via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >> Hi all, >> >> I need to figure out why InstrEmitter::EmitMachineNode assumes that when >> the number of outputs of a MachineSDNode is greater than the number of defs >> in the corresponding MCInstrDesc, the outputs in the difference will be >> placed into physical registers as opposed to virtual registers. >> >> The specific line in que...

...al interest. I agree that duplicating the FP opcodes should be our goal. I just wasn’t sure that was entirely possible. I’ll try adding implicit defs in the way you’ve suggested, but I’m concerned that there may be code that relies on the TII for that kind of thing -- for instance, InstrEmitter::EmitMachineNode() does this: bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; where “NumDefs” comes from TII and “NumResults” comes from the node. Obviously we can fix that up as needed, but it seems like a weak point in the design. Perhaps it is still better than tryin...

...ister. >>> >>> Cheers, >>> -Quentin >>> >>> On Nov 18, 2019, at 6:21 PM, Thomas Lively via llvm-dev < >>> llvm-dev at lists.llvm.org> wrote: >>> >>> Hi all, >>> >>> I need to figure out why InstrEmitter::EmitMachineNode assumes that when >>> the number of outputs of a MachineSDNode is greater than the number of defs >>> in the corresponding MCInstrDesc, the outputs in the difference will be >>> placed into physical registers as opposed to virtual registers. >>> >>> The...

Yes, the target does not have 64-bit GPRs. But it still needs to support 64-bit address space. Cheers, Iftekhar On Tue, Jul 8, 2014 at 1:19 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- > > From: "Iftekhar Chowdhury" <iftekhar.hc at gmail.com> > > To: llvmdev at cs.uiuc.edu > > Sent: Tuesday, July 8, 2014 1:06:44 PM >

..._PAIR. > >> However, when I try to insert such nodes into the DAG within > >> TriCoreTargetLowering, I run into an assertion: > >> > >> llc: > >> /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: > >> void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, > >> llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion > >> `NumMIOperands >= II.getNumOperands() && NumMIOperands <= > >> II.getNumOperands()+II.getNumImplicitDefs() && "#operands for dag > >&gt...

On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen wrote: > On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote: > > > RegScavenger is complaining about use of an undefined register, CTR8, in > > the BCTR8 instruction, in the following instance (this is from the PPC > > backend): > > > > BB#38: derived from LLVM BB %for.end50 > > Predecessors

On Aug 27, 2010, at 11:53 AMPDT, Yuri wrote: > On 08/27/2010 11:32, Yuri wrote: >> As I understand only one of TCRETURNri64 and RET should be created. >> I have sources of rev.112200. >> >> Here is the stack when TCRETURNri64 instruction is created: >> #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr >> (this=0x30eb000, TID=@0x803a78940,

...mpl(void*) + 380 10 llc 0x088a8ec5 llvm::MachineInstr::MachineInstr(llvm::MCInstrDesc const&, llvm::DebugLoc, bool) + 245 11 llc 0x08899daf llvm::MachineFunction::CreateMachineInstr(llvm::MCInstrDesc const&, llvm::DebugLoc, bool) + 111 12 llc 0x0871b4a0 llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue> >&) + 512 13 llc 0x0866dfbd llvm::ScheduleDAGSDNodes::EmitSchedule(llvm::MachineBasicBlock::bundle_iterator<llvm::MachineInstr, llvm::ilist_iterator<llvm::MachineInst...

...@0x803a9f840, DL={LineCol = 0, ScopeIdx = 0}, NoImp=false) at /tmp/llvm-svn/llvm/lib/CodeGen/MachineFunction.cpp:153 #2 0x00000008028ea302 in llvm::BuildMI (MF=@0x30eb000, DL={LineCol = 0, ScopeIdx = 0}, TID=@0x803a9f840) at MachineInstrBuilder.h:147 #3 0x0000000803164513 in llvm::InstrEmitter::EmitMachineNode (this=0x7fffffff7f80, Node=0x4b6c510, IsClone=false, IsCloned=false, VRBaseMap=@0x7fffffff8050) at /tmp/llvm-svn/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:671 #4 0x00000008031f6bdf in llvm::InstrEmitter::EmitNode (this=0x7fffffff7f80, Node=0x4b6c510, IsClone=false, IsCloned=false, VRBase...

Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit integers is

On 08/27/2010 11:32, Yuri wrote: > As I understand only one of TCRETURNri64 and RET should be created. > I have sources of rev.112200. > > Here is the stack when TCRETURNri64 instruction is created: > #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr > (this=0x30eb000, TID=@0x803a78940, DL={LineCol = 0, ScopeIdx = 0}, > NoImp=false) at