Displaying 3 results from an estimated 3 matches for "emit_precossin".
2009 Sep 10
0
[PATCH 06/13] nv50: handle SEQ, SGT, SLE, SNE opcodes
...---------
1 files changed, 61 insertions(+), 30 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index e7beb26..381e396 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -790,6 +790,9 @@ emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
#define CVTOP_SAT 0x08
#define CVTOP_ABS 0x10
+/* 0x04 == 32 bit */
+/* 0x40 == dst is float */
+/* 0x80 == src is float */
#define CVT_F32_F32 0xc4
#define CVT_F32_S32 0x44
#define CVT_F32_U32 0x64
@@ -799,7 +802,7 @@ emit_prec...
2009 Jun 21
0
[PATCH] nv50: support for SLE, SNE, SEQ, SGT
...--------
1 files changed, 80 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index 16bf2f1..75c5cea 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -810,7 +810,11 @@ emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
#define CVTOP_TRUNC 0x07
#define CVTOP_SAT 0x08
#define CVTOP_ABS 0x10
+#define CVTOP_ABSRN 0x11
+/* 0x04 == 32 bit */
+/* 0x40 == dst is float */
+/* 0x80 == src is float */
#define CVT_F32_F32 0xc4
#define CVT_F32_S32 0x44
#d...
2009 Jun 21
0
[PATCH] nv50: better insn generation
...c] == src[2][i])
break;
}
- if (i == 4)
+ if (i == 4 || !dst[i])
continue;
assimilate = TRUE;
@@ -1367,48 +1379,32 @@ nv50_program_tx_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
break;
case TGSI_OPCODE_COS:
temp = temp_temp(pc);
+ rtmp = *pp_rtmp;
emit_precossin(pc, temp, src[0][0]);
- emit_flop(pc, 5, temp, temp);
- for (c = 0; c < 4; c++) {
- if (!(mask & (1 << c)))
- continue;
- emit_mov(pc, dst[c], temp);
- }
+ emit_flop(pc, 5, rtmp, temp);
break;
case TGSI_OPCODE_DP3:
temp = temp_temp(pc);
+ rtmp = *pp_rtmp;
emit_mu...