Displaying 6 results from an estimated 6 matches for "emit_flop".
2009 Jun 21
0
[PATCH] nv50: better insn generation
...if (i == 4)
+ if (i == 4 || !dst[i])
continue;
assimilate = TRUE;
@@ -1367,48 +1379,32 @@ nv50_program_tx_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
break;
case TGSI_OPCODE_COS:
temp = temp_temp(pc);
+ rtmp = *pp_rtmp;
emit_precossin(pc, temp, src[0][0]);
- emit_flop(pc, 5, temp, temp);
- for (c = 0; c < 4; c++) {
- if (!(mask & (1 << c)))
- continue;
- emit_mov(pc, dst[c], temp);
- }
+ emit_flop(pc, 5, rtmp, temp);
break;
case TGSI_OPCODE_DP3:
temp = temp_temp(pc);
+ rtmp = *pp_rtmp;
emit_mul(pc, temp, src[0][0], src[1][0]);...
2009 Jun 24
0
[PATCH] nv50: fix previous patches
...;p->cfg.fp.regs[1] & 0x08000000)) {
- pc->p->cfg.fp.regs[1] |= 0x08000000;
+ pc->iv_p->rhw = aid - 1;
+ if (!(pc->p->cfg.fp.regs[1] & (1 << 27)))
pc->iv_p->rhw = aid++;
- emit_interp(pc, pc->iv_p, NULL,
- INTERP_LINEAR);
- emit_flop(pc, 0, pc->iv_p, pc->iv_p);
- } else {
- pc->iv_p->rhw = aid - 1;
- emit_flop(pc, 0, pc->iv_p,
- &pc->attr[fcrd * 4 + 3]);
- }
+ pc->p->cfg.fp.regs[1] |= (1 << 27);
+ emit_interp(pc, pc->iv_p, NULL, INTERP_LINEAR);
+ emit_flop(pc, 0...
2009 Sep 12
0
[PATCH 10/13] nv50: proper linkage between VP and FP
...continue;
- mask |= (1 << c);
+ if ((mode & INTERP_PERSPECTIVE) && !iv) {
+ iv = *ppiv = alloc_temp(pc, NULL);
+ iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
- alloc_reg(pc, &pc->attr[n]);
+ emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
+ emit_flop(pc, 0, iv, iv);
- pc->attr[n].rhw = (*aid)++;
- emit_interp(pc, &pc->attr[n], iv, pc->interp_mode[i]);
-
- pc->p->cfg.fp.map[(*mid) / 4] |= oid << (8 * ((*mid) % 4));
- (*mid)++;
- pc->p->cfg.fp.regs[1] += 0x00010001;
+ /* XXX: when loading interpolants dynami...
2009 May 06
2
nv50: shader generation patches
Hi ! I've been trying to improve NV50 shader generation a bit the last couple of weeks, so here is
what I've produced. I don't know if it's usable for you or just a pile of horrible hacks, but at
least it makes some mesa demos render more correcly, p.e. the teapot (aside from mip-mapping issues
of the floor texture), arbfplight, and I think the gears also didn't appear as they
2012 Apr 23
5
[Bug 49086] New: nouveau — Gallium 0 . 4 on NVA5 — 2 .1 Mesa 8.0.2 crashes Firefox Nightly
https://bugs.freedesktop.org/show_bug.cgi?id=49086
Bug #: 49086
Summary: nouveau ? Gallium 0.4 on NVA5 ? 2.1 Mesa 8.0.2 crashes
Firefox Nightly
Classification: Unclassified
Product: Mesa
Version: 8.0
Platform: x86-64 (AMD64)
OS/Version: Linux (All)
Status: NEW
Severity: normal
2009 Sep 10
0
[PATCH 06/13] nv50: handle SEQ, SGT, SLE, SNE opcodes
...(c = 0; c < 4; c++) {
- if (!(mask & (1 << c)))
- continue;
- emit_set(pc, 6, dst[c], src[0][c], src[1][c]);
- }
- break;
case TGSI_OPCODE_SIN:
if (mask & 8) {
emit_precossin(pc, temp, src[0][3]);
@@ -1626,10 +1651,16 @@ nv50_program_tx_insn(struct nv50_pc *pc,
emit_flop(pc, 4, brdc, temp);
break;
case TGSI_OPCODE_SLT:
+ case TGSI_OPCODE_SGE:
+ case TGSI_OPCODE_SEQ:
+ case TGSI_OPCODE_SGT:
+ case TGSI_OPCODE_SLE:
+ case TGSI_OPCODE_SNE:
+ i = map_tgsi_setop_cc(inst->Instruction.Opcode);
for (c = 0; c < 4; c++) {
if (!(mask & (1 << c)))...