Displaying 6 results from an estimated 6 matches for "elt0".
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2020 Jul 07
3
BUILD_VECTOR disambiguation
Hey devs,
>From ISDOpcodes.h...
/// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector
/// with the specified, possibly variable, elements. The number of elements
/// is required to be a power of two. The types of the operands must all be
/// the same and must match the vector element type, except that integer types
/// are allowed...
2020 Jul 07
3
BUILD_VECTOR disambiguation
...dev
> > Sent: Tuesday, July 7, 2020 9:53 AM
> > To: LLVM Developers Mailing List <llvm-dev at lists.llvm.org>
> > Subject: [EXT] [llvm-dev] BUILD_VECTOR disambiguation
> >
> > Hey devs,
> >
> > From ISDOpcodes.h...
> >
> > /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector
> > /// with the specified, possibly variable, elements. The number of elements
> > /// is required to be a power of two. The types of the operands must all be
> > /// the same and must match the vector element type, except that...
2020 Jul 07
2
BUILD_VECTOR disambiguation
...evelopers Mailing List <llvm-dev at lists.llvm.org>
> > > > Subject: [EXT] [llvm-dev] BUILD_VECTOR disambiguation
> > > >
> > > > Hey devs,
> > > >
> > > > From ISDOpcodes.h...
> > > >
> > > > /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width
> > > > vector /// with the specified, possibly variable, elements. The
> > > > number of elements /// is required to be a power of two. The types
> > > > of the operands must all be /// the same and must match the ve...
2019 Apr 04
5
[RFC] Changes to llvm.experimental.vector.reduce intrinsics
Hi all,
While working on a patch to improve codegen for fadd reductions on AArch64, I stumbled upon an outstanding issue with the experimental.vector.reduce.fadd/fmul intrinsics where the accumulator argument is ignored when fast-math is set on the intrinsic call. This behaviour is described in the LangRef (https://www.llvm.org/docs/LangRef.html#id1905) and is mentioned in
2016 Mar 25
0
lowering of BUILD_VECTOR
...element instruction which inserts an element from a
GPR to a Vector Register at a given index, i..e
vset <vector register> <gpr> <index>
at the moment my target only supports v4i32.
a comment for BUILD_VECTOR in the ISDOpcodes.h "says" the following:
/// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
/// specified, possibly variable, elements.
my questions are:
1. what are those elements?
2. i presume that elements can be of different types, i.e. register,
immediate, something else (don't know what). am i correct?
3. will the handling of BU...
2016 Nov 04
2
[RFC] Supporting ARM's SVE in LLVM
...sc, bool NoNaN) const;
Value* getReductionIntrinsic(IRBuilder<> &Builder,
const RecurrenceDescriptor& Desc, bool NoNaN,
Value* Src) const;
```
# SelectionDAG Nodes
## *ISD::BUILD_VECTOR* {#isdbuildvector}
`BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...)`
This node takes as input a set of scalars to concatenate into a single vector.
By its very nature this node is incompatible with scalable vectors because
we don't know how many scalars it will takes to fill one. All common code
using this node has either been rewritten...