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eliminateredundantspills
2016 Dec 22
1
Spill hoisting on RAL: looking for some debugging ideas
...s links in each loop separately into
fi#0, but with it, it moves both spills up. In architectures like
AARCH64 there are a plenty of callee-saved registers and this bug can
not be easily reproduced, so I am trying to understand why spill
hoisting do such things in mine case.
I found InlineSpiller::eliminateRedundantSpills that seems to be in
charge. I traced code down to problem. First time it hoists vreg19 ok.
Second time it sees MI, created first time, sees slot index, but then
on line:
if (LI->getVNInfoAt(Idx) != VNI) continue;
it continues.
(gdb) p *VNI
$21 = {id = 4, def = {lie = {Value = 260284292}}}
(...