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All, I just committed r185596 which removes some exception-related ISD opcodes. If you have an out-of-tree target that supports DWARF exception handling, that probably broke your build. Just delete these lines from your XXXISelLowering.cpp file: - setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); - setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); The lowering code for DWARF landing pads now only needs these parameters: setExceptionPointerRegister(X86::EAX); setExceptionSelectorRegister(X86::EDX); Thanks, /jakob

...le? Then I compiled with llc: $ llc -march=arm -mcpu=cortex-a8 -mtriple=arm-none-eabi exception.clang.ll -o exception.clang.s It doesn't generate the tables because ARMELFMCAsmInfo doesn't set ExceptionsType. If I set it to Dwarf and fix the missing lowering operations (EXCEPTIONADDR and EHSELECTION), it does generate a table which is slightly different than what GCC is doing. I've compared the assembly generated and it's close, but not perfect. Some EABI issues (frame pointer, some intrinsics mismatch, EH call table) were present, but the general execution flow seems very similar. I...