Displaying 13 results from an estimated 13 matches for "eh_labels".
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eh_label
2015 Apr 24
2
[LLVMdev] RFC: implicit null checks in llvm
I don't think we can expose the memory operations directly from a
semantic, theoretical point of view. Whether practically we can do
this or not is a different question.
Does LLVM do optimizations like these at the machine instruction
level?
if (condition)
T = *X // normal load, condition guards against null
EH_LABEL // clobbers all
U = *X // implicit null check, branches
2015 Apr 24
2
[LLVMdev] RFC: implicit null checks in llvm
On Thu, Apr 23, 2015 at 5:17 PM, Andrew Trick <atrick at apple.com> wrote:
> The scheduler itself doesn’t move anything around labels. But any pass can
> perform code motion or load/store optimization. Also, any pass can insert
> an instruction, like a copy, between the label and the load.
>
> I’m not really sure how EH_LABEL ends up translating into exception
> tables,
2015 Apr 23
2
[LLVMdev] RFC: implicit null checks in llvm
...rt
> instructions wherever it wants without looking for labels.
>
> I think labels are only employed just before code emission. Is there any
> existing example of labels being used earlier (I think GCRootLowering is
> the earliest)?
>
SelectionDAGBuilder::lowerInvokable() inserts EH_LABELs into the DAG for
normal invokes, and it more or less works out.
I don't know much about what transformations MI passes typically do, but my
guess is that you're concerned that some pass might re-schedule possibly
trapping operations inside the label range?
-------------- next part --------...
2014 Nov 06
2
[LLVMdev] Should the MachineVerifier accept a MBB with a single (landing pad) successor?
Hi all,
I've been investigating a machine verifier failure on the attached
testcase, and I'm tempted to say the verifier is wrong and should
accept it. Skip the description for the proposed change.
On AArch64, the verifier complains with:
*** Bad machine code: MBB exits via unconditional branch but
doesn't have exactly one CFG successor! ***
- function: t4
- basic
2014 Jul 26
2
[LLVMdev] Finding previous emitted instruction
Hi All,
For various obscure reasons I'd like to detect the condition when X86 CALL
instruction immediately precedes a function epilogue in the final emitted
code, and insert a NOP between them if that happens.
My initial attempt at it looked like this:
MachineBasicBlock& MBB;
MachineBasicBlock::iterator MBBI; <-- points to where the epilogue would
be inserted
if (MBBI != MBB.begin()
2008 Oct 13
0
[LLVMdev] api changes in llvm 2.4
Hi,
Chris Lattner wrote:
> In the 2.3 release, we included a list of the major LLVM API changes. If you
> are working on upgrading your code from 2.3 to 2.4, I'd appreciate it if you
> could compile a list of the major stumbling blocks you have, so that others
> can benefit from your experience. Please send any info to the list, thanks!
No major stumbling blocks during our
2008 Oct 11
2
[LLVMdev] api changes in llvm 2.4
In the 2.3 release, we included a list of the major LLVM API changes.
If you are working on upgrading your code from 2.3 to 2.4, I'd
appreciate it if you could compile a list of the major stumbling
blocks you have, so that others can benefit from your experience.
Please send any info to the list, thanks!
-Chris
2016 Dec 21
1
setjmp/longjmp and volatile stores, but non-volatile loads
On Sun, Dec 18, 2016 at 11:58 PM, Jonas Maebe <jonas-devlists at watlock.be>
wrote:
>
> Actually, there's another —even more fundamental— problem: the longjmp
> will always restore the non-volatile registers to the contents they had
> at the start of the try-block, which is not what LLVM expects when
> entering an SEH-based landing pad.
>
The SjLjEHPrepare pass tries
2014 Apr 07
6
[LLVMdev] Proposal: Loads/stores with deterministic trap/unwind behavior
...machine instructions. This
will definitely be the case for the Go frontend that I'm working with, as
its IR tends to use struct loads/stores quite frequently. So I'm not sure
if this will work. I think it needs to look a lot like how the lowering for
invokes currently looks, with a pair of EH_LABELs around a set of ordinary
load/store MIs -- which is how I implemented it.
Thanks,
--
Peter
2011 Aug 04
0
[LLVMdev] RFC: Exception Handling Rewrite
Hi Peter,
Thanks for pointing this out. Some us who are concerned with codegen have discussed the problem. Although the details aren't decided, you can be sure that at the MachineInstr level we won't have a landindpadInst to model liveness of exception values. Any physical registers set by the personality function will be considered live immediately after the call on the unwind path.
2011 Aug 04
4
[LLVMdev] RFC: Exception Handling Rewrite
Chris,
it is goodness that the LandingpadInst will be pinned to
the beginning
of a BasicBlock,... except for the possibility of PHINode
instructions that _must_
come even earlier.?.
I can't exactly put my finger on what's going to go wrong with this,
but it sure smells fishy...
my current understanding is that the LandingpadInst will "define"
some hard
2015 Apr 23
4
[LLVMdev] RFC: implicit null checks in llvm
On Wed, Apr 22, 2015 at 11:44 PM, Andrew Trick <atrick at apple.com> wrote:
>
> This feature will keep being requested. I agree LLVM should support it,
> and am happy to see it being done right.
+1
> > I plan to break the design into two parts, roughly following the
> > statepoint philosophy:
> >
> > # invokable @llvm.(load|store)_with_trap intrinsics
2014 Apr 01
6
[LLVMdev] Proposal: Loads/stores with deterministic trap/unwind behavior
Hi,
I wanted to propose an IR extension that would allow us to support zero-cost
exception handling for non-call operations that may trap. I wanted to start
with loads and stores through a null pointer, and later we might extend this to
div/rem/mod zero. This feature is obviously useful for implementing languages
such as Java and Go which deterministically translate such operations into