Displaying 12 results from an estimated 12 matches for "efer_sce".
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_efer_sce
2010 Aug 05
3
[PATCH 08/14] Nested Virtualization: efer
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
--
---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632
_______________________________________________
Xen-devel mailing list
2010 May 04
0
[PATCH] svm: support EFER.LMSLE for guests
...hvm/hvm.c 2010-05-04 13:26:07.000000000 +0200
@@ -590,6 +590,7 @@ static bool_t hvm_efer_valid(uint64_t va
((sizeof(long) != 8) && (value & EFER_LME)) ||
(!cpu_has_nx && (value & EFER_NX)) ||
(!cpu_has_syscall && (value & EFER_SCE)) ||
+ (!cpu_has_lmsl && (value & EFER_LMSLE)) ||
(!cpu_has_ffxsr && (value & EFER_FFXSE)) ||
((value & (EFER_LME|EFER_LMA)) == EFER_LMA));
}
@@ -641,7 +642,8 @@ static int hvm_load_cpu_ctxt(struct doma
}
if ( !hvm_efe...
2007 Aug 09
1
[PATCH] svm: allow guest to use EFER.FFXSE and EFER.LMSLE
...pu_has_lmsl = 1;
+#endif
+
/* SVM feature flags */
u32 svm_feature_flags;
@@ -190,7 +195,10 @@ static enum handler_return long_mode_do_
case MSR_EFER:
/* Offending reserved bit will cause #GP. */
#ifdef __x86_64__
- if ( (msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE)) ||
+ if ( (msr_content & ~(EFER_FFXSE | EFER_LMSLE | EFER_LME | EFER_LMA |
+ EFER_NX | EFER_SCE)) ||
+ (!cpu_has_lmsl && (msr_content & EFER_LMSLE)) ||
+ (!cpu_has_ffxsr && (msr_content & EFER_FFXSE)) ||
#els...
2007 Aug 08
2
[PATCH] x86-64: syscall/sysenter support for 32-bit apps
...k_eip;
+#endif
+ }
#ifdef CONFIG_COMPAT
else
{
@@ -1292,7 +1309,9 @@ void context_switch(struct vcpu *prev, s
local_flush_tlb_one(GDT_VIRT_START(next) +
FIRST_RESERVED_GDT_BYTE);
- if ( !is_pv_32on64_vcpu(next) == !(efer & EFER_SCE) )
+ if ( (!is_pv_32on64_vcpu(next)
+ || (next->arch.syscall32_callback_cs & ~3)) ==
+ !(efer & EFER_SCE) )
write_efer(efer ^ EFER_SCE);
}
#endif
Index: 2007-08-08/xen/arch/x86/traps.c
================================...
2007 Jan 31
7
[PATCH][SVM] remove FFXSR CPUID bit for AMD-V HVM guests
Remove visibility of the FFXSR CPUID bit to an HVM guest.
This patch allows HVM Windows x64 to install/boot on AMD-V platforms.
This patches applies cleanly to xen-unstable 13743.
Please apply to xen-unstable/3.0.5.
If possible, pls apply to xen-3.0.4-testing.
--Tom
thomas.woller@amd.com
AMD Corporation
5204 E. Ben White Blvd. UBC1
Austin, Texas 78741
+1-512-602-0059
2007 Apr 18
1
No subject
...3 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define E...
2007 Apr 18
1
No subject
...3 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define E...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...3 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define E...
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...3 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
+
+/* EFER bits: */
+#define _EFER_SCE 0x00000000 /* SYSCALL/SYSRET */
+#define _EFER_LME 0x00000008 /* Long mode enable */
+#define _EFER_LMA 0x0000000a /* Long mode active (read-only) */
+#define _EFER_NX 0x0000000b /* No execute enable */
+
+#define EFER_SCE (1<<_EFER_SCE)
+#define EFER_LME (1<<_EFER_LME)
+#define E...
2013 Sep 23
57
[PATCH RFC v13 00/20] Introduce PVH domU support
This patch series is a reworking of a series developed by Mukesh
Rathor at Oracle. The entirety of the design and development was done
by him; I have only reworked, reorganized, and simplified things in a
way that I think makes more sense. The vast majority of the credit
for this effort therefore goes to him. This version is labelled v13
because it is based on his most recent series, v11.
2007 Apr 18
1
[RFC/PATCH LGUEST X86_64 03/13] lguest64 core
...>rbx, val);
+ break;
+ case MSR_GS_BASE:
+ val = (vcpu->guest_gs_a & ((1UL << 32)-1)) |
+ (vcpu->guest_gs_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_FS_BASE:
+ lhwrite_u64(vcpu, regs->rbx, 0);
+ break;
+ case MSR_EFER:
+ val = EFER_SCE | EFER_LME | EFER_LMA | EFER_NX;
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ default:
+ kill_guest_dump(vcpu, "bad read of msr %llx\n", regs->rdx);
+ }
+ break;
+ case LHCALL_WRMSR:
+ switch (regs->rdx) {
+ case MSR_KERNEL_GS_BASE:
+ if ((regs->rbx >= HVVM_S...
2007 Apr 18
1
[RFC/PATCH LGUEST X86_64 03/13] lguest64 core
...>rbx, val);
+ break;
+ case MSR_GS_BASE:
+ val = (vcpu->guest_gs_a & ((1UL << 32)-1)) |
+ (vcpu->guest_gs_d << 32);
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ case MSR_FS_BASE:
+ lhwrite_u64(vcpu, regs->rbx, 0);
+ break;
+ case MSR_EFER:
+ val = EFER_SCE | EFER_LME | EFER_LMA | EFER_NX;
+ lhwrite_u64(vcpu, regs->rbx, val);
+ break;
+ default:
+ kill_guest_dump(vcpu, "bad read of msr %llx\n", regs->rdx);
+ }
+ break;
+ case LHCALL_WRMSR:
+ switch (regs->rdx) {
+ case MSR_KERNEL_GS_BASE:
+ if ((regs->rbx >= HVVM_S...