Displaying 4 results from an estimated 4 matches for "ef0fffff".
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2018 Sep 04
1
[PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
...rr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 122
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000e000-0000efff
Memory behind bridge: ee000000-ef0fffff
Prefetchable memory behind bridge: 00000000d0000000-00000000e1ffffff
The memory behind bridge at ee000000 is included in the mtrr region
reg00 which is 0xc0000000 to 0xffffffff.
Same for the prefetchable memory behind bridge.
The nvidia GPU which becomes unresponsive is:
01:00.0 3D controll...
2018 Aug 24
2
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...el Corporation Sunrise Point-LP PCI
Express Root Port [8086:9d10] (rev f1) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 120
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000e000-0000efff
Memory behind bridge: ee000000-ef0fffff
Prefetchable memory behind bridge: 00000000d0000000-00000000e1ffffff
Capabilities: [40] Express Root Port (Slot+), MSI 00
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Capabilities: [90] Subsystem: ASUSTeK Computer Inc. Sunrise
Point-LP PCI Express Root Port [1043:1a00]...
2018 Aug 24
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...int-LP PCI
> Express Root Port [8086:9d10] (rev f1) (prog-if 00 [Normal decode])
> Flags: bus master, fast devsel, latency 0, IRQ 120
> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> I/O behind bridge: 0000e000-0000efff
> Memory behind bridge: ee000000-ef0fffff
> Prefetchable memory behind bridge: 00000000d0000000-00000000e1ffffff
> Capabilities: [40] Express Root Port (Slot+), MSI 00
> Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
> Capabilities: [90] Subsystem: ASUSTeK Computer Inc. Sunrise
> Point-LP PCI Expr...
2018 Sep 04
2
[PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
On Mon, Sep 3, 2018 at 8:12 PM, Mika Westerberg
<mika.westerberg at linux.intel.com> wrote:
> We have seen one similar issue with LPSS devices when BIOS assigns
> device BARs above 4G (which is not the case here) and it turned out to
> be misconfigured MTRR register or something like that. It may not be
> related at all but it could be worth a try to dump out MTRR registers of