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2013 Sep 19
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
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2013 Sep 19
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, LLVM,
I found LLVM codegen has 3 passes for instruction scheduling:
1) pre-ra sched
2) post-ra sched
3) mi sched.
for RISC machines, there are data hazard cases appear only after Register
Allocation(RA). for example, $t0 is used immediately after writing(RAW):
ld $t0, MEM
add $t2, $t0, $0
There may be one or more stall in pipeline. Instruction scheduler can
detect this kinds of conflict