search for: earlyclob

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2014 Aug 01
2
[LLVMdev] initialize register attributes in instruction definition
...like this? or some other way in codegen to make the register flags are set up based on the instructions? >> >> let Constraints = “$dst.SC_X =1, $src.SC_Y =0" in > > This isn't what Constraints are for. Constraints can be either tied > operands e.g. $dst = $src or @earlyclober $dst, meaning that the $dst > may be written before all source registers are read. > > Can you explain more about what you are trying to do? It looks like you > might be trying to force an instruction to uses a specific component of > a vector register. > Yes, that is pretty...
2014 Jul 31
3
[LLVMdev] initialize register attributes in instruction definition
Hi All, Is it possible to initialize(set up) register attributes when we define an instruction? like if a register is defined like this: " class SC_Register<bits<8> register_num, REG_FLAG SC_X, REG_FLAG SC_Y, REG_FLAG SC_Z, REG_FLAG SC_W, string asmstr> : Register<asmstr> { let HWEncoding{7-0} =