search for: e6e6c004

Displaying 2 results from an estimated 2 matches for "e6e6c004".

2019 Apr 17
2
Disable combining of loads and stores in instcombine
...ry model, it makes sense to elide multiple loads to the same memory location between barriers.; IIRC the semantics for volatile don’t allow this eliding. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190417/e6e6c004/attachment.html>
2019 Apr 17
2
Disable combining of loads and stores in instcombine
So, volatile’s been a fine solution — the issue is volatile pointers would perform the load every time; ideally memory accesses would be able to be cached. This is why I’ve been leaning towards disabling the part of instcombine that combines memory accesses instead of using volatile — there should be better performance. On Apr 17, 2019, 9:54 AM -0700, Jameson Nash <vtjnash at gmail.com>,