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e40cbdd4
2014 Sep 30
2
[LLVMdev] Behaviour of NVPTX intrinsic
Have a look at how the ARM backend handles the CPSR register. It sounds like
what you're really looking for is liveness of that status register not to be
clobbered between the arithmetic instruction you're inspecting and the
instruction that reads that register.
Cheers,
Jon
On 9/30/14 12:39 PM, Jingyue Wu wrote:
> I can't think of any NVPTX intrinsic that disallow even