search for: e185

Good day. Suddenly on pretty high loaded pool with about 50 VM per 5 hosts I got following problem vm does not start and start command silently waiting. xe task-list displays pack of tasks with same status and resident-on: uuid ( RO) : b607ef7b-e185-72d9-4d3a-5795557922fc name-label ( RO): VM.start name-description ( RO): subtask_of ( RO): <not in database> subtasks ( RO): resident-on ( RO): e9dc1da9-178b-4a98-8dd2-571a920cd4cc status ( RO): pending pr...

...n of loop headers - 3 of them in one single function. the patch applies and compiles with svn trunk, it also works for the small testcase, but i did not run the testsuites. florian -- Brandner Florian CD Laboratory - Compilation Techniques for Embedded Processors Institut für Computersprachen E185/1 Technische Universität Wien Argentinierstraße 8 / 185 A-1040 Wien, Austria Tel.: (+431) 58801-58521 E-Mail: brandner at complang.tuwien.ac.at -------------- next part -------------- A non-text attachment was scrubbed... Name: tailup-loop.c Type: text/x-csrc Size: 149 bytes Desc: not availab...

...feedback, Jakob and Evan. Gergo -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...gt; Gergo > -- > Gergö Barany, research assistant gergo at complang.tuwien.ac.at > Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: +43-1-58801-58522 > Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...his might have changed in the meantime. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

Hello everybody, we noticed that llvmgcc4.2-2.2 sometimes generates non-natural loops when compiling to bytecode without any optimizations. Apparently what happens is that the loop header is duplicated, which results in two entry points for the loop. Since this could obstruct subsequent loop optimizations, it might be interesting to further investigate this behavior. To show the problem, I have

A more pressing need is a pre-regalloc scheduler that can switch modes to balance reducing latency vs. reducing register pressure. The problem is the current approach is the scheduler is locked into one mode or the other. For x86, it generally makes sense to schedule for low register pressure. That is, until you are dealing with a block that are explicitly SSE code in 64-bit mode. In that case,

...ecessary conversion instructions. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

...> patch > applies and compiles with svn trunk, it also works for the small > testcase, > but i did not run the testsuites. > > florian > > -- > Brandner Florian > > CD Laboratory - Compilation Techniques for Embedded Processors > Institut für Computersprachen E185/1 > Technische Universität Wien > > Argentinierstraße 8 / 185 > A-1040 Wien, Austria > > Tel.: (+431) 58801-58521 > > E-Mail: brandner at complang.tuwien.ac.at > > <tailup-loop.c><taildup- > loopheader.patch>___________________________________________...

...n instructions. > > -- > Gergö Barany, research assistant > gergo at complang.tuwien.ac.at > Institute of Computer Languages > http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: > +43-1-58801-58522 > Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: > +43-1-58801-18598 > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100829/24246c54/attachment.html>

...4f 5051 5253 5455 5657 5859 5a5b LMNOPQRSTUVWXYZ[ 00000050: 5c5d 5e5f 6061 6263 6465 6667 6869 6a6b \]^_`abcdefghijk 00000060: 6c6d 6e6f 7071 7273 7475 7677 7879 7a7b lmnopqrstuvwxyz{ 00000070: 7c7d 7e7f ffad 9b9c 9da6 aeaa f8f1 fde6 |}~............. 00000080: faa7 afac aba8 8e8f 9280 90a5 999a e185 ................ 00000090: a083 8486 9187 8a82 8889 8da1 8c8b a495 ................ 000000a0: a293 94f6 97a3 9681 989f e2e9 e4e8 eae0 ................ 000000b0: ebee e3e5 e7ed fc9e f9fb ecef f7f0 f3f2 ................ 000000c0: a9f4 f5c4 b3da bfc0 d9c3 b4c2 c1c5 cdba ................ 000000d0:...

Hello list, I wonder if llvm/Clang can compile C or C++ for ARM from on x86. http://comments.gmane.org/gmane.comp.compilers.clang.devel/8896 The talk above answered 'NO' to my question, which means Clang is not yet able to cross compile for ARM on X86. Is the answer still correct for my question? I saw somewhere that Clang supports ARM on Darwin only. Then is the cross compiling

Hi, Paul Curtis wrote: > If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this

Hello, is it possible to compile just an subproject? For example, just llc or lli? Cheers. Beckert. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120503/c20aa7b1/attachment.html>

Hello Everyone, Would you please send me any links to documentation on LLVM stack? I am particularly interested in knowing how each instruction in an LLVM bit code file(.ll file) affects its stack. To be specific, is it possible to map an LLVM program as operations on a stack? Thanks, Amruth

Thanks andrew for the answer. I would like to generate code for Cortex-A9 that don't use neon for fp computation but vfpv3 -d16. I've tried some combination of -mattr=+neon,-neonfp,+vfp3,+d16 but couldn't get ".fpu vfpv3-d16" directive generated in assembly file. Do you know how to make it happen ? Best Regards Seb From: Andrew Trick [mailto:atrick at apple.com] Sent:

All, I apologize if this is an inappropriate question for this mailing list. If so, please recommend an appropriate place to post the question. I'm also somewhat new to LLVM, so I could have some pretty fundamental misunderstandings about what I am trying to do. I have searched for information on the llvm.org website (user's guide, programmer's manual and doxygen documentation),

...array of the given number of elements. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598

...ting problems ;-) > > -- > Gergö Barany, research assistant > gergo at complang.tuwien.ac.at > Institute of Computer Languages > http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: > +43-1-58801-58522 > Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: > +43-1-58801-18598 > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121011/3a31c97e/attachment.html>