search for: e1.3

Displaying 20 results from an estimated 98 matches for "e1.3".

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2014 Sep 08
2
[LLVMdev] Alias Analysis - ModRefBehaviour
Hello, Is there a analysis pass which calculates the ModRefBehaviours OnlyReadsPointerArguments and OnlyAccessesPointerArguments? I tried to find one but so far I only saw that different AA's return OnlyReadsMemory and DoesNotAccessMemory if the readonly and readnone attributes are set. Best regards and thanks in advance, Johannes -- Johannes Doerfert Researcher / PhD Student
2017 Mar 13
2
[llvm-devmeeting] [EuroLLVM] Hacker's Lab - Topics and Volunteers needed!
Registered, thx! On 03/13, Renato Golin wrote: > On 13 March 2017 at 13:01, Tobias Grosser <tobias.grosser at inf.ethz.ch> wrote: > > I am happy to merge these things. > > Ok. We'll need a big table. :) -- Johannes Doerfert Researcher / PhD Student Compiler Design Lab (Prof. Hack) Saarland Informatics Campus, Germany Building E1.3, Room 4.31 Tel. +49 (0)681
2014 Sep 20
2
[LLVMdev] How to translate library functions into LLVM IR bitcode?
Hi Johannes, Actually, I'm working in the same scenario, i.e. configure + make of a benchmark/program/library like you said. I've got your point of using this script as a replacement to generate .bc files instead of a executable. That's truly helpful and has already answered my original question. Now I'm actually moving a step further. Take the same example in your reply, say, if
2016 Apr 12
2
ScalarEvolution "add nsw" question
Hi Johannes, Sanjoy has given you great information already. On Sun, Apr 10, 2016 at 5:19 PM, Sanjoy Das <sanjoy at playingwithpointers.com> wrote: > Johannes Doerfert wrote: > > Is there any plan to use e.g., post-dominance information to > > propagate wrapping flags? > > None that I'm aware of. > > > If x +nsw y post-dominates the entry block > >
2017 Jan 20
2
[RFC] IR-level Region Annotations
On 01/11, Daniel Berlin via llvm-dev wrote: > > > > def int_experimental_directive : Intrinsic<[], [llvm_metadata_ty], > > [IntrArgMemOnly], > > "llvm.experimental.directive">; > > > > def int_experimental_dir_qual : Intrinsic<[], [llvm_metadata_ty], > > [IntrArgMemOnly], > >
2019 Jan 31
6
[RFC] Vector Predication
Hi, There is now an RFC for a roadmap to native vector predication support in LLVM and a prototype implementation:   https://reviews.llvm.org/D57504 The prototype demonstrates: -  Predicated vector intrinsics with an explicit mask and vector length parameter on IR level. -  First-class predicated SDNodes on ISel level. Mask and vector length are value operands. -  An incremental strategy
2016 Sep 20
2
Differential: accepted but not closed revisions
Hi! There are a lot of accepted but not closed revisions in Differential. Many of them were actually committed, but without Differential revision link or when it was specified in wrong way. I think will be good idea to create script which will match committed revisions with those in Differential: file list should be same and hashes of changed line could be calculated for each file. In case of
2014 Sep 20
2
[LLVMdev] How to translate library functions into LLVM IR bitcode?
Hi Johannes, By following your directions, I can use your script as is to produce the .bc file now. Here's my command line for compiling s_sin.c into s_sin.bc file and the output: command line: ~/Downloads/newlib-2.1.0/newlib/libm/mathfp » python ~/llvm_link.py s_sin.c -I../common/ -I../../libc/include/ -o s_sin.bc output: Initiate CLANG (/path-to-clang): Options: 's_sin.c
2015 Feb 09
2
[LLVMdev] [lld] Need help: "buildbot failure in LLVM on lld-x86_64-freebsd"
Hey, I was just informed that my ScalarEvolution patch failed the lld tests on x86_64-freebsd, however on my machine x86_64-linux all tests (llvm+lld) pass for a debug as well as a release build. Furthermore, I'm a bit confused about the error message just before the segfault happens: "Unable to find lib.exe in PATH" Could somebody help me track down the problem? Thanks in
2019 Feb 01
3
[RFC] Vector Predication
Hi, On 1/31/19 11:20 PM, Jacob Lifshay wrote: > We're in-progress designing a RISC-V extension > (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) > that would have variable-length vectors of short vectors (1 to 4): > <VL x <4 x float>> > where each predicate bit masks out a whole short vector. We're using > this extension
2017 Mar 24
2
[EuroLLVM] Hacker's Lab - Topics and Volunteers needed!
Hi Christian, We put your name down for an exception handling table at the same time & room as the ARM (32/64) table [Renato]. I hope this is OK with you. Thanks! -- Johannes On 03/24, Christian Bruel wrote: > Hello, > > If there is a table on Exception handling, Can I have a slot in the agenda > to discuss a proposal to clarify and adapt the attributes used to handle the
2017 Mar 08
4
(no subject)
".... the problem Mehdi pointed out regarding the missed initializations of array elements, did you comment on that one yet?" What is the initializations of array elements question? I don't remember this question. Please refresh my memory. Thanks. I thought Mehdi's question is more about what are attributes needed for these IR-annotation for other LLVM pass to understand and
2018 Jun 11
2
Question about the status of the IR extensions for OpenMP
[Apologies if you received this email twice, the first time I sent it from the wrong email account] Hi all, some time ago Intel proposed a set of minimal IR extensions to improve the support of OpenMP in LLVM [1][2]. I wonder if there has been any progress on this and if it is going to be upstreamed. Also the previous proposal[2] and communications to the llvm-dev[3] mention the following
2019 Feb 07
2
[RFC] Vector Predication
Jacob Lifshay <programmerjake at gmail.com> writes: > So it would be handy for the vector length on evl intrinsics to be in > units of the mask length so we don't have to pattern match a division > in the backend. We could have 2 variants of the vector length > argument, one in terms of the data vector and one in terms of the mask > vector. we could legalize the mask
2019 Feb 08
5
[RFC] Vector Predication
On Thu, Feb 7, 2019, 09:21 Simon Moll <moll at cs.uni-saarland.de> wrote: > > On 2/7/19 6:08 PM, David Greene wrote: > > Jacob Lifshay <programmerjake at gmail.com> writes: > > > >> So it would be handy for the vector length on evl intrinsics to be in > >> units of the mask length so we don't have to pattern match a division > >> in the
2017 Mar 08
5
(no subject)
<mehdi.amini at apple.com>, Bcc: Subject: Re: [llvm-dev] [RFC][PIR] Parallel LLVM IR -- Stage 0 -- IR extension Reply-To: In-Reply-To: <20170224221713.GA931 at arch-linux-jd.home> Ping. PS. Are there actually people interested in this? We will continue working anyway but it might not make sense to put it on reviews and announce it on the ML if nobody cares. On 02/24,
2017 Mar 08
3
(no subject)
> On Mar 8, 2017, at 10:55 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> >> On Mar 8, 2017, at 5:36 AM, Johannes Doerfert <doerfert at cs.uni-saarland.de> wrote: >> >> <mehdi.amini at apple.com>, >> Bcc: >> Subject: Re: [llvm-dev] [RFC][PIR] Parallel LLVM IR -- Stage 0 -- IR extension >> Reply-To: >>
2019 Feb 04
4
[RFC] Vector Predication
On 2/2/19 1:39 AM, Luke Kenneth Casson Leighton wrote: > > > On Friday, February 1, 2019, Simon Moll <moll at cs.uni-saarland.de > <mailto:moll at cs.uni-saarland.de>> wrote: > > We could untie the mask length from the data length: > >   %result = call <scalable 4 x float> > @llvm.evl.fsub.v4f32(<scalable 4 x float> %x, <scalable 4
2016 Nov 16
2
Highlighting trailing whitespaces on Phab?
So, I forwarded the request for highlighting trailing whitespaces to phabricator upstream (https://secure.phabricator.com/T11879), and upstream folks suggest we enable the Lint feature in Arcanist ( https://secure.phabricator.com/book/phabricator/article/arcanist_lint/). This will enforce the check when `arc diff` is run (reviewers wouldn't see the warnings though). There are two linters we
2015 Sep 13
4
Dynamic detection of signed integer overflow
Hello, I thought about doing a dynamic detection of signed integer overflow for OpenCL kernels based on the generated LLVM IR. A problem seems to be that the LLVM IR does not differentiate between signed and unsigned types in general. But for instance for additions it should be possible to use the "nsw" flag as indicator that the operations involves signed types. Is this a legal