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...How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: girish gulawani <girishvg at yahoo.com> >Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Wednesday, 21 December 2011 12:41 AM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > >Hi Girish, > >Sorry, but I'm afraid I don't understand your question. C...

...(Dest), from lib/CodeGen/LiveIntervalAnalysis.cpp. Certainly those addReg seems to be done wrongly. Any hint as to what must be the correct steps? Thanks. Girish. From: Jim Grosbach <grosbach at apple.com> >To: girish gulawani <girishvg at yahoo.com> >Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Wednesday, 21 December 2011 11:30 PM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > >Ah, OK. I think I understand much better now. Thanks! You shouldn't need bun...

...ub triad. > > How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: girish gulawani <girishvg at yahoo.com> > Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Sent: Wednesday, 21 December 2011 12:41 AM > Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > Hi Girish, > > Sorry, but I'm afraid I don't understand your questi...

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > >Hi Johannes, > >You may be interested in the (very) recently added explici...

...On Dec 19, 2011, at 9:12 PM, girish gulawani wrote: > > Hello Jim. > Just out of curiosity, won't such mechanism work via the patterns from instructions defs? > > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> > Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Sent: Monday, 19 December 2011 10:33 PM > Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > Hi Johannes, > > You may be interested in the (very) recently added e...

On Thu, Oct 27, 2011 at 9:29 AM, Johannes Birgmeier <e0902998 at student.tuwien.ac.at> wrote: > >> Hi Johannes, what processor are you targeting?  Is it little-endian or >> big-endian? > Little-endian. (The truth: you can set it manually, but it is set to > little endian, for sure.) The processor is a TI TMS320C64x. > > Follow-up...

On Sat, Jan 7, 2012 at 10:18 AM, Johannes Birgmeier <e0902998 at student.tuwien.ac.at> wrote: > Hello, > > my target has libcall support for long long shifts. I already have the > following lines in my Lowering constructor: > >   setLibcallName(RTLIB::SHL_I64, "__llshl"); >   setLibcallName(RTLIB::SRL_I64, "__llshru&quot...

> Hi Johannes, what processor are you targeting? Is it little-endian or > big-endian? Little-endian. (The truth: you can set it manually, but it is set to little endian, for sure.) The processor is a TI TMS320C64x. Follow-up: I discovered that the "guilty" method is DAGCombiner::ReduceLoadWidth. The error is introduced because the offset is not calculated correctly. The first

On Sun, Jan 8, 2012 at 2:37 AM, Johannes Birgmeier <e0902998 at student.tuwien.ac.at> wrote: >> Is i64 a legal type on your target?  If so, you might need to hack the >> code generator a bit; no in-tree target has a legal integer type that >> doesn't support shifts.  If not, I have no idea how you're getting >> that error....

Hi Johannes, You may be interested in the (very) recently added explicit instruction bundle support. For an example of their usage, have a look at the ARM backend's IT-block (Thumb2 predication support) pass, which uses them to tie instructions together. -Jim On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated

Hello, my target has libcall support for long long shifts. I already have the following lines in my Lowering constructor: setLibcallName(RTLIB::SHL_I64, "__llshl"); setLibcallName(RTLIB::SRL_I64, "__llshru"); setLibcallName(RTLIB::SRA_I64, "__llshr"); and setOperationAction(ISD::SHL, MVT::i64, Expand); setOperationAction(ISD::SRA, MVT::i64,

Hello, I'm writing for a backend and have a complicated instruction bundle (3 instructions) that has to be executed like a single block (meaning: if the first instruction is executed, all three have to be executed to obtain the result, though not necessarily without other instructions in between). Unfortunately, MachineCSE gets in the way sometimes and rips it apart. Is there a way to

> Is i64 a legal type on your target? If so, you might need to hack the > code generator a bit; no in-tree target has a legal integer type that > doesn't support shifts. If not, I have no idea how you're getting > that error. Yes, well, i64 is a legal type, that's how it is. However, i64s are always stored in two 32-bit registers and in some cases need complicated

Hello, is there a way to formulate a constraint like this: let Constraints = "${src:sub_even} != $dst" in { ... } , that is, only if a subregister of $src != $dst then ...? Perhaps this is entirely the wrong way anyway. I'm trying to implement (s/z/any)ext & trunc from 32 to 64 bit integer on a TI C64x processor. 64 bit ints are always stored in two adjacent registers (not

> This is contradictory: on a little-endian processor, the address for > loading a 64-bit value is same as the address of the low word. Are > you sure you're modeling the semantics of your lddw and stddw > instructions correctly? ... I thought so until now. Because I implemented stdw (store doubleword) completely analogous to lddw: Just print out stdw with the given pointer and

Hello! I have the following simple IR: ================================== @l = common global i64 0, align 8 define void @hello() nounwind { entry: store i64 -4919131755279862989, i64* @l ret void } define i32 @main(i32 %argc, i8** %argv) nounwind { entry: call void @hello() %tmp = load i64* @l %conv = trunc i64 %tmp to i32 ret i32 %conv } ==================================

Hello! Is there a way to tell LLVM how to emulate an instruction with multiple others? Specifically, in our processor, there is no instruction for adding two i64s; it has to be done like this dst_high32:dst_low32 = src1_low32 + src2_low32 (unsigned add; dst_high might contain the overflow bit) dst_high32 = dst_high32 + src1_high32 dst_high32 = dst_high32 + src2_high32 I tried it with

>> Yes, well, i64 is a legal type, that's how it is. However, i64s are >> always stored in two 32-bit registers and in some cases need complicated >> instruction patterns for easy things (such as add, sub and so on) that >> basically simulate the i64 behaviour with a sequence of i32 >> instructions. > I think you're misunderstanding what it means for a type