search for: dylanmckay34

...on and so fourth. ​ On Sat, Jan 30, 2016 at 8:54 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> >> >> On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> >> wrote: >> >>> Try visualising the DAG like this. >>> >>> ``` >>> ---- GPR:$rA >>> / >>> set GPR:$rd ---- add >>> \ >>>...

Hello all, I have submitted and merged patches for most of the public modifications required for the AVR backend, and I am amount to start the process of adding the lib/Target/AVR directory piece by piece. As this will be a significant portion of code (~7000 lines), it should have a code owner. I have been working on the backend for the last year, maintaining it, overseeing contributions, and

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >> \ >> ---- GPR:$rB >> ```...

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with...

...treat that as a broad ‘no objection’ by the community. Are there any other active contributors to the AVR back end? David > On 27 Oct 2015, at 09:41, Dylan McKay via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Ping. > > On Fri, Oct 23, 2015 at 4:04 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Hello all, > > I have submitted and merged patches for most of the public modifications required for the AVR backend, and I am amount to start the process of adding the lib/Target/AVR directory piece by piece. > > As this will be a significant portion of c...

Are you primarily trying to avoid Expand being implemented as a lib call with a larger type? No - I’m stuck in this situation: - 8-bit addition is legal - 16-bit addition is illegal, should expand into an add and an add with carry - A few operations support 16-bit operands - the 16-bit DREGS register class The legalizer sees that 16-bit addition should expand. It sees that there

...the search entry. This will give you a list of the commits, and resolutions. From my understanding ( NO Expert ), a large part of the skeleton code has been added. The leave the rest of the skeleton,and all the fleshy bits. Good progress Dylan!. On Mon, Dec 21, 2015 at 3:28 AM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Hey Allen, > > Progress is slow but it is happening. It will take a number of more > releases until it is ready. > > Currently the backend is marked as an 'experimental' target, which means > the only way it can be used is by compiling LLVM fr...

What is the meaning of a $ sign in tablgen? Here is an example // Pattern fragments def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), (MipsVExtractSExt node:$vec, node:$idx, i8)>; Taken from https://github.com/llvm-mirror/llvm/blob/fd031a51c35d1781c066a42e221a7ae28610be3f/lib/Target/Mips/MipsMSAInstrInfo.td#L118 -- Rail Shafigulin

...odeLDSTPtrReg"; } I am able to use it in the place of PTRREGS in the definition of the LD instruction, but if I use it in an instruction matching pattern, compilation fails with the error "Unknown leaf kind: LDSTPtrReg:i16:$ptrreg". On Sun, Feb 1, 2015 at 10:26 AM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > You could probably create a new >> Operand subclass with a custom EncoderMethod that gets assigned to >> both the dddd and the odd field > > Ah, I hadn't realised that the encoder method had access to the containing > instruction. > > I b...

How is the llvm-avr backend integration going ? Will it be functional ( experimental ) in the 3.8 release ? Will Clang recognize options for avr ? thanks. Allen -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151218/be23dc42/attachment.html>

I am working on an LLVM backend for the AVR architecture, and am having troubles working with the codegen layer, trying to get around the quirks of the binary encodings of the AVR ISR. There are several different families of AVR microcontrollers, each with a minimum 'core' instruction set. Each family builds upon (or removes) the core ISR with more instructions or different encodings. My

I'm confused about how to specify DAG patterns for a given instruction Here is an example for my target class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode> : ALU_RR<subOp, asmstr, [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>; def ADD : ALU1_RR<0x0, "l.add", add>; The set operation simply creates a list. The add operation

> As far as I know, you cannot define a tablegen pattern with multiple results, and need to use C++ matching. I’m kind of surprised there are defined td nodes for these. Yes they were added a while ago, but never used. If I write a C++ matcher, will the register allocator work correctly? The multiplication instruction I'm working with always writes the result to registers `R1` and `R0`,

I'm attempting to implement codegen support for the AVR ST/LD <http://www.atmel.com/webdoc/avrassembler/avrassembler.wb_ST.html> family of instructions. The binary encoding is not particularly consistent -- take a look at this table of variants of LD, along with their machine code representation: # load 8 bits from pointer register X into general purpose Rd ld Rd, X `1001 000d dddd

Hey all, The AVR backend has now finally been merged in-tree completely. Thanks to Krzysztof and Matt for all of their hard work reviewing patches <https://reviews.llvm.org/differential/query/AuHaJ3SXjDmO> Development will now halt on the downstream repository (on GitHub <https://github.com/avr-llvm/llvm>), and it will now be done LLVM proper. This is good news, especially for the

Hello all, I am working on adding atomics support to the AVR backend. Because the target can only have one core, it is sufficient to: - Save the status register - Disable interrupts - Do the nonatomic LOAD/STORE/SWAP/ADD - Restore the status register I’d really like to be able to do this at the IR level. What I want to do is write a custom lowering hook to convert ISD::ATOMIC_LOAD