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...e the exist from a function to a call-site must match the entry from the corresponding call-site. The problem is a simple balanced parentheses problem in CFL-reachability, and it can be computed efficiently. The paper you mentioned is a very nice paper that proposed an efficient algorithm to solve Dyck-CFL-reachability problem in bidirectional graphs. However, precise pointer analysis cannot be formulated as a Dyck-CFL-reachability problem. The alias analysis presented in that paper is an over approximation. Hence the time bound from our paper still applies. Regards, Lian On Fri, Oct 18, 20...

On Tuesday, July 20, 2010 4:04 PM, Jakob Stoklund Olesen > > On Jul 20, 2010, at 10:57 AM, Ken Dyck wrote: > > > Does anybody have any tips for generating spills/reloads for large > > non-vector registers? > > [snip] > > > This is quite simple to handle. A register > MachineOperand has a subreg field for this > purpose. It is used to pick out subregisters >...

...#39;m still interested in using XNgine::LoadFromMemory to access my stack variables but I wonder what someone more experienced would do ; Will this cover all of the bases ? ; Can I reference metadata at (or near) the pointer returned by 'alloca' to get the info I need ? thanks , dane van dyck georgia institute of technology

...airly old paper next to that that essentially gives a >O(1) query time bound for this, but your problem exactly fits into the bidirectional graph problem, unless i'm missing something. > > The paper you mentioned is a very nice paper that proposed an > efficient algorithm to solve Dyck-CFL-reachability problem in > bidirectional graphs. Right, and your matching call sites can be formulated as one. However, precise pointer analysis cannot be > formulated as a Dyck-CFL-reachability problem. FWIW: This remains to be seen, and certainly also depends on your definitions of...

I'd also like to register my disappointment that the slides and videos aren't available. On Friday, October 16, 2009 4:46 PM, David Greene wrote: > When I agreed to be a speaker, I signed off on having my > talk made publicly available. There does seem to be a > double-standard here and that's concerning. There are few things about this whole situation that aren't

Hi, One of the long-standing code clean-up bugs in Bugzilla is to extract the Machine* code from the CodeGen library into a separate one, on which CodeGen depends ( http://llvm.org/bugs/show_bug.cgi?id=1121). I'd like to start working on this. The general approach I'm planning to take is: 1. Identify which code to move. 2. Eliminate all dependencies that the Machine code has on the

On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > Would there be any interest/opposition to extending the set of simple > integer types in MVT to include the missing multiples of 8 (up to 64 > bits)? That is: i24, i40, i48, i56? > > Adding the types to MVT (and ValueTypes.td) would allow LLVM to be > targeted to archite...

On Wednesday, December 02, 2009 7:09 PM, Chris Lattner wrote: > > On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > > > Would there be any interest/opposition to extending the set > of simple > > integer types in MVT to include the missing multiples of 8 > (up to 64 > > bits)? That is: i24, i40, i48, i56? > > > > Adding the types to MVT (and ValueTypes.td) wou...

The architecture that I'm targeting with an LLVM back end has SRA instructions for all its data sizes, but is missing SRL instructions for some data sizes. I'm having trouble with the SelectionDAGISel::ShrinkDemandedOps() pass. Although it runs after the DAG has been legalized, it replaces legal SRAs with illegal SRLs, which results in failures in instruction selection. Is there a

Hello, On a recent discussion on the cfe-dev mailing list[1] it was asked how easy it was to create a backend to an Harvard Arch chip: different data/function pointer sizes and 16 bit chars (main issues of the targeted arch). Ken Dyck has posted a patch (which solved at least the second problem of 16bit char) on which I have been working on and Douglas Gregor said that different pointer sizes are already supported by Clang, but what about llvm? When creating a backend, I have created the DataLayout string but this string only al...

On Wednesday, July 21, 2010 11:21 AM, Jakob Stoklund Olesen wrote: > > On Jul 21, 2010, at 7:44 AM, Ken Dyck wrote: > > Speaking of the rewriter, I've had some > problems recently where the > > rewriter replaces the last of the three > load instructions with a COPY > > instruction because isLoadFromStackSlot() > returns the same frame index > > for all three load. For...

Two functions in DwarfDebug, addBlockByrefAddress() and addComplexAddress(), contain this snippet of code: // Decode the original location, and use that as the start of the byref // variable's location. const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false); DIEBlock *Block = new (DIEValueAllocator) DIEBlock();

On Jan 18, 2011, at 7:01 AM, Ken Dyck wrote: > Should addBlockByrefAddress() and addComplexAddress() be doing the same? Yes. Can you prepare a patch ? Thanks, - Devang

Am 08.03.2011 um 19:59 schrieb Ken Dyck: > If you are interested, I can send you a patch of the changes that I > made to the 2.8 release for a backend that targets a 24-bit > word-addressable DSP, but it is quite rough and it includes changes in > which you probably aren't interested (support for non-power-of-2 > inte...

Hi, I did the Pass ID workaround by providing Passes.h in the include/llvm/Machine. But the question which is holding me up is that, as Ken Dyck was kind enough to point out, what should be done to the dependency on libAnalysis? The Machine passes are not only dependent on Passes class but also on others such as the ConstantFolding.h. Is it a possible solution to break this dependency or carry this dependency to the Machine library as well?...

I recently subscribed to the bugs mailing list and submitted a suspected bug. The report seems to be ignored. I am guessing that it is being ignored because I am not actually an asterisk user and I am unable to supply the version or configuration of the suspect site. So then I thought I should get an account for one of the forums. I tried repeatedly to create an account but it always told me

...rror timed out> Trying other mirror. continues until it runs out of mirrors. I'm able to access everything, ie: ping google.com lynx google.com is fine. I've tried halting iptables (I'm behind router) all to no avail. Any help would be appreciated. ron -- ================= Ron Dyck pulpfree1 at gmail.com www.webbtech.net ================= -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.centos.org/pipermail/centos/attachments/20070621/cad1cebf/attachment-0001.html>

...boxes when using this testbox as a nameserver. The named.conf and zone files were copied from another local development box with RH 8 installed. I am of course pointing to the test box to use as DNS server in my workstation tcp/ip config. Any help would be appreciated. -- ================= Ron Dyck pulpfree1 at gmail.com www.webbtech.net =================

On Jul 20, 2010, at 10:57 AM, Ken Dyck wrote: > Does anybody have any tips for generating spills/reloads for large > non-vector registers? > > I'm working on a back end for a DSP architecture that has accumulator > registers that are too large to be spilled or reloaded with a single > instruction. All of their bi...

On Wed, Sep 11, 2013 at 12:29 AM, Andrew Trick <atrick at apple.com> wrote: > > If that is the goal, then you only want the modules for Machine IR, and maybe some core analysis passes. The “Machine” modules you listed above include machine code analysis or transform passes that you probably don’t want. Pruning the list to basic IR support: > >> - MachineBasicBlock >> -