search for: dw_op_piece

Displaying 3 results from an estimated 3 matches for "dw_op_piece".

2011 Jul 07
2
[LLVMdev] Debug with DW_OP_piece and DW_OP_bit_piece
We are running into trouble with debug information in that we have registers along with sub registers, and they both point to the same dwarf register. Does LLVM support the DW_OP_piece/bit_piece debug information when allocating a sub-register from a super register? If not, is there any plan to add it? If not, would it be difficult to add? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/at...
2011 Jul 07
0
[LLVMdev] Debug with DW_OP_piece and DW_OP_bit_piece
On Jul 7, 2011, at 12:08 PM, Villmow, Micah wrote: > We are running into trouble with debug information in that we have registers along with sub registers, and they both point to the same dwarf register. Does LLVM support the DW_OP_piece/bit_piece debug information when allocating a sub-register from a super register? If not, is there any plan to add it? If not, would it be difficult to add? It would not be too difficult to add for your target. Today, ARM code gen supports this. See ARMAsmPrinter::EmitDwarfRegOp(). - Devang ---...
2019 Nov 15
4
DW_OP_implicit_pointer design/implementation in general
On Fri, Nov 15, 2019 at 8:07 AM Robinson, Paul <paul.robinson at sony.com> wrote: > | Any ideas why it wouldn't be more general to handle cases where the > variable isn't named? > > > > Couldn’t there be a DIE (flagged as artificial) to describe the > return-value temp? > There could be - though there are very few (the array bound example Adrian gave is the