search for: dvfs

Hi, This is a try to have some simple DVFS (Dynamic Voltage and Frequency Scaling) support for GK20A. Instead of relying on other existing frequency scaling framework, we create a simple subdev in Nouveau for the same purpose. That's because we don't want to make the DVFS implementation for GK20A far more than enough in the beginnin...

On Thu, Dec 18, 2014 at 4:28 PM, Vince Hsu <vinceh at nvidia.com> wrote: > This patch creates a subdev for DVFS (Dynamic Voltage and Frequency Scaling) > support in Nouveau. This subdev refers to the status information provided by > the NVIDIA hardware and tries to adjust the performance level based on the > calculated target. Only the GK20A is supported right now. Hey Vince, I'd not make a new...

...Thu, Dec 18, 2014 at 8:13 PM, Vince Hsu <vinceh at nvidia.com> wrote: > Hello Ben, > > On 12/18/2014 05:34 PM, Ben Skeggs wrote: >> >> On Thu, Dec 18, 2014 at 4:28 PM, Vince Hsu <vinceh at nvidia.com> wrote: >>> >>> This patch creates a subdev for DVFS (Dynamic Voltage and Frequency >>> Scaling) >>> support in Nouveau. This subdev refers to the status information provided >>> by >>> the NVIDIA hardware and tries to adjust the performance level based on >>> the >>> calculated target. Only the G...

This patch creates a subdev for DVFS (Dynamic Voltage and Frequency Scaling) support in Nouveau. This subdev refers to the status information provided by the NVIDIA hardware and tries to adjust the performance level based on the calculated target. Only the GK20A is supported right now. Signed-off-by: Vince Hsu <vinceh at nvidia.co...

Hello Ben, On 12/18/2014 05:34 PM, Ben Skeggs wrote: > On Thu, Dec 18, 2014 at 4:28 PM, Vince Hsu <vinceh at nvidia.com> wrote: >> This patch creates a subdev for DVFS (Dynamic Voltage and Frequency Scaling) >> support in Nouveau. This subdev refers to the status information provided by >> the NVIDIA hardware and tries to adjust the performance level based on the >> calculated target. Only the GK20A is supported right now. > Hey Vince, > &...

...On Thu, Dec 18, 2014 at 8:13 PM, Vince Hsu <vinceh at nvidia.com> wrote: >> Hello Ben, >> >> On 12/18/2014 05:34 PM, Ben Skeggs wrote: >>> On Thu, Dec 18, 2014 at 4:28 PM, Vince Hsu <vinceh at nvidia.com> wrote: >>>> This patch creates a subdev for DVFS (Dynamic Voltage and Frequency >>>> Scaling) >>>> support in Nouveau. This subdev refers to the status information provided >>>> by >>>> the NVIDIA hardware and tries to adjust the performance level based on >>>> the >>>> calcu...

Hi, All, I have some problem of using dvfs in Xen 3.4.1 and 2.6.18 kernel. I enabled Speed option in BIOS and add "cpufreq=xen" in the grub file. But when I entered my dom0 and type "xenpm get-cpufreq-XXX" (any xenpm argument), it returns "[CPU0] failed to get CPU P state". I am wondering if I should enable...

Hi, All, I have some problem of using dvfs in Xen 3.4.1 and 2.6.18 kernel. I enabled Speed option in BIOS and add "cpufreq=xen" in the grub file. But when I entered my dom0 and type "xenpm get-cpufreq-XXX" (any xenpm argument), it returns "[CPU0] failed to get CPU P state". I am wondering if I should enable...

Hello, I want to use DVFS in xen. I use Fedora 8. The server supports DVFS when it boots from Fedora 8 without xen. Then, I installed Xen 3.4 from source and boots successfully. But the cpufreq directory is gone in the system. I cannnot use DVFS. If I run xenpm get-cpufreq-xxx, it always reports "failed to get xxx&quot...

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...moment is that having this information in the driver is fine. I >>> have added a few other NVIDIA people to gather thoughts. >> >> The voltage<->frequency relationship is per chip, not per board. We read >> the chip id at runtime, and programmatically determine the DVFS steps >> based on that. CVB table contains the parameters for the algorithm. >> >> I think the table belongs in the driver. The table is not per board, and >> the values in CVB table do not describe hardware, but parameters to an >> algorithm. > > In that case I...

...ncies, my gut feeling for > the moment is that having this information in the driver is fine. I > have added a few other NVIDIA people to gather thoughts. The voltage<->frequency relationship is per chip, not per board. We read the chip id at runtime, and programmatically determine the DVFS steps based on that. CVB table contains the parameters for the algorithm. I think the table belongs in the driver. The table is not per board, and the values in CVB table do not describe hardware, but parameters to an algorithm. Terje -------------------------------------------------------------...

On 07/10/2014 06:50 PM, Mikko Perttunen wrote: > Does GK20A itself have any kind of thermal protection capabilities? > Upstream SOCTHERM support is not yet available (though I have a driver > in my tree), so we are thinking of disabling CPU DVFS on boards that > don't have always-on active cooling for now. Same might be necessary for > GPU as well. There is a small thermal driver ( https://android.googlesource.com/kernel/tegra/+/b445e5296764d18861a6450f6851f25b9ca59dee/drivers/video/tegra/host/gk20a/therm_gk20a.c ) but it does...

...lid time commitment that warrants being a mentor. Of course, the mentor does not necessarily have to have the deepest understanding of the subject matter. *At the end of the GSOC* a good student should be trusted with having more knowledge on the specific topic than the mentor. That being said, DVFS is fidgetty and the outcome is binary (it either works or crashes your machine spectacularly), so it's difficult to get someone started and keep 'em motivated if as a mentor you don't have experience on the topic. As such, I'd consider it a high risk topic to promote unless one...

...for >> the moment is that having this information in the driver is fine. I >> have added a few other NVIDIA people to gather thoughts. > > The voltage<->frequency relationship is per chip, not per board. We read > the chip id at runtime, and programmatically determine the DVFS steps > based on that. CVB table contains the parameters for the algorithm. > > I think the table belongs in the driver. The table is not per board, and > the values in CVB table do not describe hardware, but parameters to an > algorithm. In that case I also think it would make more...

...hat > warrants being a mentor. > Of course, the mentor does not necessarily have to have the deepest > understanding of the subject matter. *At the end of the GSOC* a good > student should be trusted with having more knowledge on the specific > topic than the mentor. That being said, DVFS is fidgetty and the outcome > is binary (it either works or crashes your machine spectacularly), so > it's difficult to get someone started and keep 'em motivated if as a > mentor you don't have experience on the topic. As such, I'd consider it > a high risk topic to pro...

Does GK20A itself have any kind of thermal protection capabilities? Upstream SOCTHERM support is not yet available (though I have a driver in my tree), so we are thinking of disabling CPU DVFS on boards that don't have always-on active cooling for now. Same might be necessary for GPU as well. On 10/07/14 10:34, Alexandre Courbot wrote: > This series adds support for reclocking on GK20A. The first two patches touch > the clock subsystem to allow GK20A to operate, by making th...

On Tue 2019-03-26 @ 10:40:49 AM, Ilia Mirkin wrote: > Just looked over the projects... they all seem valid Thank you for taking the time to have a look and provide feedback! > but are there > people who could realistically mentor a GSoC student for these? IMHO > unless mentors can be identified, these should all be archived. Attracting mentors is probably the hardest part of running

There might be some callers of nouveau_clock_astate(), and they are from inetrrupt context. So we must ensure that this function can be atomic in that condition. This patch adds one parameter which is subsequently passed to nouveau_pstate_calc(). Therefore we can choose whether we want to wait for the pstate work's completion or not. Signed-off-by: Vince Hsu <vinceh at nvidia.com> ---

Hello Vince, Op 28-11-14 om 12:57 schreef Vince Hsu: > Hi Roy, > > On 11/28/2014 07:25 PM, Roy Spliet wrote: >> Hello Vince, >> >> One minor question inline. >> >> Op 28-11-14 om 12:13 schreef Vince Hsu: >>> The voltage value are calculated by the hardware characterized >>> result. >>> >>> Signed-off-by: Vince Hsu