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...rgets. The reason I am posting to this list is that a GHC compiled program (using the LLVM backend) is getting an illegal instruction exception on the this instruction: ldr r0, [r0] According to the Arm archtecture manual: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489i/CIHGJHED.html this is pre-indexed load instruction of the form: LDR{type}{cond} Rt, [Rn, #offset] but is illegal because the pre-indexed form of this instruction does not allow 'Rt' and 'Rn' to be the same register. The above all makes sense, but I find it a little hard to b...

...n the realm of pattern-matching. > > The inverse form (always propagating NaNs) is not widely natively > supported. > > I think AArch64 *might* have it? > It does. In fact, even armv7 has a NaN-propagating min/max: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489i/CIHDEEBE.html -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140912/932d64f4/attachment.html>

> On Sep 12, 2014, at 10:27 AM, Dan Gohman <dan433584 at gmail.com> wrote: > > > More generally, I don’t see a compelling reason for LLVM to add intrinsic support for the version you’re proposing. Your choice can easily be expanded into IR, and does not have the wide hardware support (particularly in GPUs) that the IEEE version does. > > The IEEE version can also be