Displaying 6 results from an estimated 6 matches for "dtripl".
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dtriple
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
> This isn't really my area of expertise, but I think you're messing up
> your RegisterClass definition. Look at how ARM defines DTriple.
DTriple is untyped :) , because we do not have any valut type which
defines 3xi64.
However, the paired register needs to have type.
Fabian, what are the definitions of ER and DR register classes?
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg St...
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...t;
> 5. GetCostForDef crashes here, as getRepRegClassFor(VT /* == MVT::i64
> */) returns NULL:
>
> RegClass = TLI->getRepRegClassFor(VT)->getID();
This isn't really my area of expertise, but I think you're messing up
your RegisterClass definition. Look at how ARM defines DTriple.
-Eli
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
2012/8/21 Anton Korobeynikov <anton at korobeynikov.info>:
>> This isn't really my area of expertise, but I think you're messing up
>> your RegisterClass definition. Look at how ARM defines DTriple.
> DTriple is untyped :) , because we do not have any valut type which
> defines 3xi64.
> However, the paired register needs to have type.
>
> Fabian, what are the definitions of ER and DR register classes?
Hi Anton,
here are the definitions of these register classes:
// Data reg...
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
2012/8/20 Eli Friedman <eli.friedman at gmail.com>:
> On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler
> <fabian.scheler at gmail.com> wrote:
>> Hi Eli,
>>
>>>>>> 2. Storing arbitrary sized integers
>>>>>>
>>>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for
>>>>>>
2014 Mar 26
19
[LLVMdev] 3.4.1 Release Plans
Hi,
We are now about halfway between the 3.4 and 3.5 releases, and I would
like to start preparing for a 3.4.1 release. Here is my proposed release
schedule:
Mar 26 - April 9: Identify and backport additional bug fixes to the 3.4 branch.
April 9 - April 18: Testing Phase
April 18: 3.4.1 Release
How you can help:
- If you have any bug fixes you think should be included to 3.4.1, send
me an
2013 Aug 08
14
[LLVMdev] [global-isel] Proposal for a global instruction selector
...PR. (i8, v1i8, v2i4, v4i2, v8i1)
All 16-bit types via ldrh/strh to GPR. (i16, f16, v1i16, v2i8, ...)
All 32-bit types via ldr/str to GPR and vldr/vstr to SPR.
All 64-bit types via ldrd/strd to GPRPair and vldr/vstr to DPR.
All 128-bit types via vld1/vst1 to DPair.
All 192-bit types via vld1/vst1 to DTriple.
All 256-bit types via vld1/vst1 to DQuad.
This larger set of legal types also makes it easier to handle things like extractelement <8 x i8> which currently produces an illegal type and is thus obfuscated by the type legalizer.
An i8 live range could exist in an ARM function as long as the...