Displaying 14 results from an estimated 14 matches for "dstrc".
2014 Oct 30
2
idmap weirdness - wildcard values being used instead of rfc2307 AD values
...f research on this and haven't been able to solve the
problem. Hopefully someone here has a better understanding of this than I
do.
The problem is that the UIDs and GIDs are not being fetched from AD. For
example "getent passwd doug" returns:
doug:*:70003:70005:Doug Meredith:/home/DSTRC/doug:/bin/false
My full name has correctly been pulled from AD but the UID specified in AD
is 20001 and the group is 10000. The values shown above are obviously
coming from the wildcard idmap specified in my smb.conf, but I'm at a loss
as to why. This occurs for all users and all groups.
Pl...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...ate
> // a new virtual register and copy the value into it, but first attempt to
> // shrink VReg's register class within reason. For example, if VReg == GR32
> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
> if (II) {
> const TargetRegisterClass *DstRC = nullptr;
> if (IIOpNum < II->getNumOperands())
> DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
> if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
> unsigned NewVReg = MRI->createVirtualRegister(Dst...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...er and copy the value into it, but first attempt
>> to
>> // shrink VReg's register class within reason. For example, if VReg ==
>> GR32
>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>> if (II) {
>> const TargetRegisterClass *DstRC = nullptr;
>> if (IIOpNum < II->getNumOperands())
>> DstRC =
>> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>> if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
>> unsigned NewVReg = MRI->...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...new virtual register and copy the value into it, but first attempt to
>> // shrink VReg's register class within reason. For example, if VReg == GR32
>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>> if (II) {
>> const TargetRegisterClass *DstRC = nullptr;
>> if (IIOpNum < II->getNumOperands())
>> DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>> if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
>> unsigned NewVReg = MRI->createVir...
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> I'm trying to do something like this:
>
> // Dst = NewVReg's reg class
> // *II = MCInstrDesc
> // IIOpNum = II Operand Num
>
> if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC)
> MRI->setRegClass(VReg, DstRC);
> else
> BuildMI(... TargetOpcode::COPY...)
>
> The condition is trying to reset the reg class if the DstRC reg class is valid for the operand num of the machine instructio...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...k VReg's register class within reason. For example, if
>>>>>>> VReg == GR32
>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>>>>>>> if (II) {
>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>> DstRC =
>>>>>>> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>>>>>>> if (DstRC && !MRI->constra...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...ister class within reason. For example, if
>>>>>>>> VReg == GR32
>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>>>>>>>> if (II) {
>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>>> DstRC =
>>>>>>>> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>>>>>>>> if (DstRC &&...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...in reason. For example, if
>>>>>>>>> VReg == GR32
>>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>>>>>>>>> if (II) {
>>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>>>> DstRC =
>>>>>>>>> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>>>>>>>>> if (D...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...gt;>> VReg == GR32
>>>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to
>>>>>>>>>> GR32_NOSP.
>>>>>>>>>> if (II) {
>>>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>>>>> DstRC =
>>>>>>>>>> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>>>>>>>>&g...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...== GR32
>>>>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to
>>>>>>>>>>> GR32_NOSP.
>>>>>>>>>>> if (II) {
>>>>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>>>>>> DstRC =
>>>>>>>>>>> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>>>>>&g...
2011 Mar 22
0
[LLVMdev] sitofp inst selection in x86/AVX target [PR9473]
...TSI2SD definition from
isAsmParserOnly = 0 into isAsmParserOnly = 1 block so that existing
VCVTSI2SD definition takes effect only in asm parser.
Example solution is as follows.
lib/Target/X86/x86InstrSSE.td
...
multiclass sse12_vcvt_avx_s<bits<8> opc, RegisterClass SrcRC,
RegisterClass DstRC,
SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
string asm> {
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
[(set DstRC:$dst, (OpNode SrcRC:$src))]>;
def rm : SI<opc, MRMSrcMem, (outs...
2014 Mar 27
0
FreeBSD winbind UID/GID mapping weirdness
.... On FreeBSD I am given a value from the 70000 range specified as the
wildcard mapping. I am using exactly the same smb.conf on both systems.
This same behavior is shown for all groups and users.
wbinfo -g and wbinfo -u works on both hosts.
The smb.conf is as follows:
[global]
workgroup = DSTRC
security = ADS
realm = DSTRC.ORG
encrypt passwords = yes
idmap config *:backend = tdb
idmap config *:range = 70001-80000
idmap config DSTRC:backend = ad
idmap config DSTRC:schema_mode = rfc2307
idmap config DSTRC:range = 500-40000
winbind nss info = rfc2307
winbind t...
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 22, 2015, at 9:10 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> One last question regarding this please.
>
> Why aren't we simply changing the register class in AddRegisterOperand instead of building a new COPY? I admit I haven't thought this out but for my test cases so far this works just fine and reduces the number of ASM mov instructions that are
2009 Apr 28
1
[LLVMdev] Register class intersection
...ed by B.SpillAlignment
This would introduce two new subclass chains:
RFP80 subclass of RFP64 subclass of RFP32
VR128 subclass of FR64
Define intersection as described above:
intersection(A, B) = max { X | X subclass-eq A, X subclass-eq B }
The coalescer can then use NewRC = intersection(SrcRC, DstRC). This
gives the same result for the existing targets, and it works correctly
for blackfin and other future targets.
The subclass relation can be seen as adding constraints on a virtual
register. If A is a subclass of B, it is always legal to change a
virtual register class from B to A. Th...