Displaying 20 results from an estimated 35 matches for "dst0".
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2016 Mar 16
2
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...*
> bool raw;
> uint8_t slot; // $surface index
> };
> std::vector<Resource> resources;
> + */
>
> struct MemoryFile {
> uint8_t mem_type; // TGSI_MEMORY_TYPE_*
> @@ -1423,8 +1425,8 @@ private:
> void handleLIT(Value *dst0[4]);
> void handleUserClipPlanes();
>
> - Symbol *getResourceBase(int r);
> - void getResourceCoords(std::vector<Value *>&, int r, int s);
> + // Symbol *getResourceBase(int r);
> + // void getResourceCoords(std::vector<Value *>&, int r, int s);
&g...
2016 Mar 17
4
[PATCH mesa v2 1/3] nouveau: codegen: Disable more old resource handling code
...ruct Resource {
uint8_t target; // TGSI_TEXTURE_*
bool raw;
uint8_t slot; // $surface index
};
std::vector<Resource> resources;
+ */
struct MemoryFile {
uint8_t mem_type; // TGSI_MEMORY_TYPE_*
@@ -1419,8 +1421,8 @@ private:
void handleLIT(Value *dst0[4]);
void handleUserClipPlanes();
- Symbol *getResourceBase(int r);
- void getResourceCoords(std::vector<Value *>&, int r, int s);
+ // Symbol *getResourceBase(int r);
+ // void getResourceCoords(std::vector<Value *>&, int r, int s);
void handleLOAD(Value *ds...
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...ruct Resource {
uint8_t target; // TGSI_TEXTURE_*
bool raw;
uint8_t slot; // $surface index
};
std::vector<Resource> resources;
+ */
struct MemoryFile {
uint8_t mem_type; // TGSI_MEMORY_TYPE_*
@@ -1423,8 +1425,8 @@ private:
void handleLIT(Value *dst0[4]);
void handleUserClipPlanes();
- Symbol *getResourceBase(int r);
- void getResourceCoords(std::vector<Value *>&, int r, int s);
+ // Symbol *getResourceBase(int r);
+ // void getResourceCoords(std::vector<Value *>&, int r, int s);
void handleLOAD(Value *ds...
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...uint8_t slot; // $surface index
>> };
>> std::vector<Resource> resources;
>> + */
>>
>> struct MemoryFile {
>> uint8_t mem_type; // TGSI_MEMORY_TYPE_*
>> @@ -1423,8 +1425,8 @@ private:
>> void handleLIT(Value *dst0[4]);
>> void handleUserClipPlanes();
>>
>> - Symbol *getResourceBase(int r);
>> - void getResourceCoords(std::vector<Value *>&, int r, int s);
>> + // Symbol *getResourceBase(int r);
>> + // void getResourceCoords(std::vector<Value *>...
2016 Apr 21
3
[PATCH mesa v2 1/3] nouveau: codegen: LOAD: Always use component 0 when getting the address
.../codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 557608e..d3c2d61 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2277,7 +2277,7 @@ Converter::handleLOAD(Value *dst0[4])
if (!dst0[c])
continue;
- Value *off = fetchSrc(1, c);
+ Value *off = fetchSrc(1, 0);
Symbol *sym;
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
--
2.7.3
2014 Nov 18
2
[PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
src0 = fetchSrc(0, c);
val0 = getScratch();
mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
- mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
+ mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
+ mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
}
break;
case TGSI_OPCODE_ROUND:
--
2.0.4
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...I_OPCODE_POW:
> case TGSI_OPCODE_SHL:
> case TGSI_OPCODE_ISHR:
> case TGSI_OPCODE_USHR:
> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
> break;
> + case TGSI_OPCODE_POW:
> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
> + break;
Can you use mk...
2013 Jan 04
2
[LLVMdev] TableGen patterns with multiple outputs
...tation in the current implementation?
If I have TableGen code like the following...
1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>;
1244
1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1),
1246 (ins Int32Regs:$a),
1247 "test $dst0, $dst1, $a;",
1248 [(set Int32Regs:$dst0, Int32Regs:$dst1,
(TestNode Int32Regs:$a))]>;
... TableGen crashes with the following stack trace:
#0...
2016 Apr 07
2
[PATCH] nouveau: codegen: Take src swizzle into account on loads
...odegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 557608e..cc51f5a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2279,12 +2279,16 @@ Converter::handleLOAD(Value *dst0[4])
Value *off = fetchSrc(1, c);
Symbol *sym;
+ uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
+
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,...
2013 Jan 07
2
[LLVMdev] TableGen patterns with multiple outputs
...>
>
> If I have TableGen code like the following...
>
> 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
> 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>;
> 1244
> 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1),
> 1246 (ins Int32Regs:$a),
> 1247 "test $dst0, $dst1, $a;",
> 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1,
> (TestNode Int32Regs:$a))]>;
>
> ... TableGen crashes with t...
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...SHL:
>>> case TGSI_OPCODE_ISHR:
>>> case TGSI_OPCODE_USHR:
>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>>> break;
>>> + case TGSI_OPCODE_POW:
>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> + mkOp1(OP_MOV, TYPE_F32, dst0[c],...
2014 Nov 18
2
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
..._from_tgsi.cpp
>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>> src0 = fetchSrc(0, c);
>> val0 = getScratch();
>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
>> }
>> break;
>> case TGSI_OPCODE_ROUND:
>>
>
> I don't understand the math behind this. For any such large...
2013 Jan 07
0
[LLVMdev] TableGen patterns with multiple outputs
...>
> If I have TableGen code like the following...
>
> 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
> 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>;
> 1244
> 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1),
> 1246 (ins Int32Regs:$a),
> 1247 "test $dst0, $dst1, $a;",
> 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>;
>
> ... TableGen crashes with the f...
2013 Jan 07
0
[LLVMdev] TableGen patterns with multiple outputs
...ve TableGen code like the following...
>>
>> 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
>> 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>;
>> 1244
>> 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1),
>> 1246 (ins Int32Regs:$a),
>> 1247 "test $dst0, $dst1, $a;",
>> 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>;
>>
>> ... TableGe...
2016 Mar 16
13
[PATCH mesa 1/6] tgsi_build: Fix return of uninitialized memory in tgsi_*_instruction_memory
tgsi_default_instruction_memory / tgsi_build_instruction_memory were
returning uninitialized memory for tgsi_instruction_memory.Texture and
tgsi_instruction_memory.Format. Note 0 means not set, and thus is a
correct default initializer for these.
Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory")
Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>
2014 Feb 20
0
[PATCH] nv50: enable txg where supported
...(TXF, TXF);
NV50_IR_OPCODE_CASE(TXQ, TXQ);
+ NV50_IR_OPCODE_CASE(TG4, TXG);
NV50_IR_OPCODE_CASE(EMIT, EMIT);
NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
@@ -2434,6 +2435,9 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
case TGSI_OPCODE_TXD:
handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
break;
+ case TGSI_OPCODE_TG4:
+ handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
+ break;
case TGSI_OPCODE_TEX2:
handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
break;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/sr...
2014 Nov 18
1
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...+2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> src0 = fetchSrc(0, c);
>>>> val0 = getScratch();
>>>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
>>>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
>>>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
>>>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
>>>> }
>>>> break;
>>>> case TGSI_OPCODE_ROUND:
>>>>
>>>
>>&g...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---
2016 Apr 07
0
[PATCH] nouveau: codegen: Take src swizzle into account on loads
...tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index 557608e..cc51f5a 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -2279,12 +2279,16 @@ Converter::handleLOAD(Value *dst0[4])
>
> Value *off = fetchSrc(1, c);
> Symbol *sym;
> + uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
> +
> if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
> off = NULL;
> sym = makeS...
2016 Apr 21
0
[PATCH mesa v2 3/3] nouveau: codegen: LOAD: Take src swizzle into account
...odegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index e2db731..01df4f3 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2279,13 +2279,17 @@ Converter::handleLOAD(Value *dst0[4])
Value *off;
Symbol *sym;
+ uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
+
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
-...