search for: dspec_cpu_lp64

Displaying 12 results from an estimated 12 matches for "dspec_cpu_lp64".

2012 Nov 06
2
[LLVMdev] Help needed on debugging llvm
...have this tricky situation - I use dragonegg generated LLVM IR as input to clang for some analysis (well it is clang++ actually). Understably,clang cribs looking at __builtin_iceil. Any idea how to resolve that as well? clang++ -O2 -march=bdver2 -mno-fma -save-temps -mfma4 -ffp-contract=fast -DSPEC_CPU_LP64 Compute.o ComputeList.o ComputeNonbondedUtil.o LJTable.o Molecule.o Patch.o PatchList.o ResultSet.o SimParameters.o erf.o spec_namd.o -o namd spec_namd.o: In function `main': spec_namd.ll:(.text+0x2a3): undefined reference to `__builtin_iceil' > Please ope...
2012 Nov 06
3
[LLVMdev] Help needed on debugging llvm
...ath option. My dragonegg is built with gcc-4.7.0 (I am compiling namd spec benchmark here again). Any idea? g++ -march=bdver2 -save-temps -fplugin=/home/anboyapa/install/bin/dragonegg.so -O2 -march=bdver2 -save-temps -fplugin=/home/anboyapa/install/bin/dragonegg.so -mno-fma -mfma4 -ffast-math -DSPEC_CPU_LP64 Compute.o ComputeList.o ComputeNonbondedUtil.o LJTable.o Molecule.o Patch.o PatchList.o ResultSet.o SimParameters.o erf.o spec_namd.o -o namd spec_namd.o: In function `main': spec_namd.C:(.text+0x2a3): undefined reference to `__builtin_iceil' collect2: error: ld r...
2012 Nov 06
0
[LLVMdev] Help needed on debugging llvm
...nalysis (well it is clang++ actually). Understably,clang cribs > looking at __builtin_iceil. Any idea how to resolve that as well? adding dragonegg support for iceil would solve both problems. Ciao, Duncan. > clang++ -O2 -march=bdver2 -mno-fma -save-temps -mfma4 -ffp-contract=fast > -DSPEC_CPU_LP64 Compute.o ComputeList.o ComputeNonbondedUtil.o LJTable.o > Molecule.o Patch.o PatchList.o ResultSet.o SimParameters.o erf.o > spec_namd.o -o namd > spec_namd.o: In function `main': > spec_namd.ll:(.text+0x2a3): undefined reference to `__builtin_iceil'...
2012 Nov 06
0
[LLVMdev] Help needed on debugging llvm
...egg is built with gcc-4.7.0 > (I am compiling namd spec benchmark here again). > Any idea? > g++ -march=bdver2 -save-temps -fplugin=/home/anboyapa/install/bin/dragonegg.so > -O2 -march=bdver2 -save-temps -fplugin=/home/anboyapa/install/bin/dragonegg.so > -mno-fma -mfma4 -ffast-math -DSPEC_CPU_LP64 Compute.o ComputeList.o > ComputeNonbondedUtil.o LJTable.o Molecule.o Patch.o PatchList.o ResultSet.o > SimParameters.o erf.o spec_namd.o -o namd > spec_namd.o: In function `main': > spec_namd.C:(.text+0x2a3): undefined reference to `__builtin_iceil' &...
2018 Aug 14
2
optimization remarks
Hi, I am trying to compare the loop vectorizers effectiveness for different targets relative to each other. That way, I am hoping to find loops that are not vectorized - but could be - on my target by finding other targets doing this successfully. With some luck, there might be something in the Target files that could be fixed with improved vectorization as a result... I would like to do
2012 Nov 05
0
[LLVMdev] Help needed on debugging llvm
Hi Anitha, > http://llvm.org/bugs/show_bug.cgi?id=14185 > I am stuck on analysis. Does any one have alternate suggestions on debugging > llvm? (Please refer to comments for the work done so far) try to reduce a small standalone testcase which is an LLVM IR (.ll) file. Ciao, Duncan.
2012 Nov 05
3
[LLVMdev] Help needed on debugging llvm
Hi, http://llvm.org/bugs/show_bug.cgi?id=14185 I am stuck on analysis. Does any one have alternate suggestions on debugging llvm? (Please refer to comments for the work done so far) -- * Anitha* -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121105/3c6b8af3/attachment.html>
2013 Jul 02
2
[LLVMdev] MI Scheduler vs SD Scheduler?
...ng error message: GCC_4.6.4_DIR/install/bin/gcc -c -o lbm.o -DSPEC_CPU -DNDEBUG    -O3 -march=core2 -mtune=core2 -fplugin='DRAGON_EGG_DIR/dragonegg.so' -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' -fplugin-arg-dragonegg-llvm-option='-pre-RA-sched:source'       -DSPEC_CPU_LP64         lbm.c cc1: for the -pre-RA-sched option: may only occur zero or one times! specmake: *** [lbm.o] Error 1 What does this message mean? Is this a bug or we are doing something wrong? How can we test the MI scheduler by itself? Is it interesting to test 3.3 or there are interesting fea...
2015 Apr 16
2
[LLVMdev] Compile SPEC2006 with clang-3.2, multi definition errors.
...etpwd-UxjZIi.o: In function `fstat64': /usr/include/sys/stat.h:498: multiple definition of `fstat64' /tmp/c-parse-7tFGiF.o:/usr/include/sys/stat.h:498: first defined here /tmp/getpwd-UxjZIi.o: In function `fstatat': ....... 2.1 ) the link commands details clang -g -DSPEC_CPU -DNDEBUG -DSPEC_CPU_LP64 -I. -DHTYU -DSPEC_CPU_LINUX alloca.bc asprintf.bc vasprintf.bc c-parse.bc c-lang.bc attribs.bc c-errors.bc c-le x.bc c-pragma.bc c-decl.bc c-typeck.bc c-convert.bc c-aux-info.bc c-common.bc c-format.bc c-semantics.bc c-objc-common.bc main.bc cpplib.bc cpplex.bc cppmacr o.bc cppexp.bc cppfiles.bc c...
2013 Jul 01
0
[LLVMdev] MI Scheduler vs SD Scheduler?
Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi, > > We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been
2013 Jul 12
0
[LLVMdev] MI Scheduler vs SD Scheduler?
...essage: > > GCC_4.6.4_DIR/install/bin/gcc -c -o lbm.o -DSPEC_CPU -DNDEBUG -O3 -march=core2 -mtune=core2 -fplugin='DRAGON_EGG_DIR/dragonegg.so' -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' -fplugin-arg-dragonegg-llvm-option='-pre-RA-sched:source' -DSPEC_CPU_LP64 lbm.c > cc1: for the -pre-RA-sched option: may only occur zero or one times! > specmake: *** [lbm.o] Error 1 > > What does this message mean? > Is this a bug or we are doing something wrong? I’m not sure why the driver is telling you this. Maybe someone familiar with drag...
2013 Jun 28
2
[LLVMdev] MI Scheduler vs SD Scheduler?
Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that