Displaying 4 results from an estimated 4 matches for "ds13".
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ds1
2019 Nov 20
4
Tablegen PAT limitation?
...;
def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add
DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10,DS11,
DS12, DS13, DS14, DS15
)>;
def uimm2 : Operand<i32>, ImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<2>;
let DecoderMethod = "decodeUImmOperand<2&...
2019 Nov 21
2
Tablegen PAT limitation?
...
def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add
DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10,DS11,
DS12, DS13, DS14, DS15
)>;
def uimm2 : Operand<i32>, ImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<2>;
let DecoderMethod = "decodeUImmOperand<2&...
2019 Nov 22
2
Tablegen PAT limitation?
...;
def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add
DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10,DS11,
DS12, DS13, DS14, DS15
)>;
def uimm2 : Operand<i32>, ImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<2>;
let DecoderMethod = "decodeUImmOperand<2&...
2019 Nov 25
2
Tablegen PAT limitation?
...)>;
def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add
DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10,DS11,
DS12, DS13, DS14, DS15
)>;
def uimm2 : Operand<i32>, ImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<2>;
let DecoderMethod = "decodeUImmOperand<2&...