search for: drm_update_vblank_count

...->vblank_time_lock, irqflags); /* + * Always update the count and timestamp to maintain the + * appearance that the counter has been ticking all along until + * this time. This makes the count account for the entire time + * between drm_crtc_vblank_on() and drm_crtc_vblank_off(). + */ + drm_update_vblank_count(dev, pipe, false); + + /* * Only disable vblank interrupts if they're enabled. This avoids * calling the ->disable_vblank() operation in atomic context with the * hardware potentially runtime suspended. @@ -332,14 +340,6 @@ void drm_vblank_disable_and_save(struct vblank->enabl...

...0 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 12.768192] CR2: 000000edb16580b8 CR3: 000000020cc09000 CR4: 00000000003406f0 > [ 12.768193] Call Trace: > [ 12.768198] ? enqueue_task_fair+0x64/0x600 > [ 12.768211] ? drm_get_last_vbltimestamp+0x47/0x70 [drm] > [ 12.768223] ? drm_update_vblank_count+0x65/0x240 [drm] > [ 12.768227] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 12.768238] ? drm_vblank_disable_and_save+0x55/0xc0 [drm] > [ 12.768250] ? drm_crtc_vblank_off+0xa9/0x1e0 [drm] > [ 12.768253] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 12.768299] ? nouveau_display_fini+0...

...001 R13: ffff8803f8471000 R14: ffffc900039f7b94 R15: ffffc900039f7bd0 ORIG_RAX: ffffffffffffffff CS: 0010 SS: 0018 #12 [ffffc900039f7b18] gf119_head_vblank_put at ffffffffa04422f9 [nouveau] #13 [ffffc900039f7b88] drm_get_last_vbltimestamp at ffffffffa020ad91 [drm] #14 [ffffc900039f7ba8] drm_update_vblank_count at ffffffffa020b3e1 [drm] #15 [ffffc900039f7c10] drm_vblank_disable_and_save at ffffffffa020bbe9 [drm] #16 [ffffc900039f7c40] drm_crtc_vblank_off at ffffffffa020c3c0 [drm] #17 [ffffc900039f7cb0] nouveau_display_fini at ffffffffa048a4d6 [nouveau] #18 [ffffc900039f7ce0] nouveau_display_suspend at fff...

...3 >>> [ 12.768192] CR2: 000000edb16580b8 CR3: 000000020cc09000 CR4: 00000000003406f0 >>> [ 12.768193] Call Trace: >>> [ 12.768198] ? enqueue_task_fair+0x64/0x600 >>> [ 12.768211] ? drm_get_last_vbltimestamp+0x47/0x70 [drm] >>> [ 12.768223] ? drm_update_vblank_count+0x65/0x240 [drm] >>> [ 12.768227] ? pci_pm_runtime_resume+0xa0/0xa0 >>> [ 12.768238] ? drm_vblank_disable_and_save+0x55/0xc0 [drm] >>> [ 12.768250] ? drm_crtc_vblank_off+0xa9/0x1e0 [drm] >>> [ 12.768253] ? pci_pm_runtime_resume+0xa0/0xa0 >>>...

...rvable under DRI2 by the Xorg.log filling with flip handler warning messages. Call drm_accurate_vblank_count() before sending out flip completion events to enforce a vblank count/ts update for the vblank of flip completion and avoid stale counts/timestamps. This fix leads to one redundant call to drm_update_vblank_count for each completed flip, but no other side effects. On a ~6 year old Core i7 M620@ 2.67GHz the redundant call costs about 10 usecs per flip Successfully tested on GeForce 9500/9600/330M so far. Signed-off-by: Mario Kleiner <mario.kleiner.de at gmail.com> Cc: Ben Skeggs <bskeggs at redhat...

...did not get a reasonable result, as such a failure wasn't considered all too horrible. There are a few NVidia gpu models out there which may need a bit more than 1 retry to get a successful query result under some conditions. Since Linux 4.4 the update code for vblank counter and timestamp in drm_update_vblank_count() changed so that the implementation assumes that high precision vblank timestamping of a kms driver either consistently succeeds or consistently fails for a given video mode and encoder/connector combo. Iow. switching from success to fail or vice versa on a modeset or connector change is ok, but s...

....474003] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 321.474004] CR2: 00007fdd82e8f810 CR3: 0000000214683000 CR4: 00000000000006e0 [ 321.474005] Call Trace: [ 321.474068] ? nv50_head_vblank_put+0x22/0x50 [nouveau] [ 321.474085] drm_get_last_vbltimestamp+0x41/0x70 [drm] [ 321.474102] drm_update_vblank_count+0x61/0x230 [drm] [ 321.474118] drm_vblank_disable_and_save+0x59/0xc0 [drm] [ 321.474134] drm_crtc_vblank_off+0x1d5/0x210 [drm] [ 321.474152] ? drm_modeset_drop_locks+0x4e/0x60 [drm] [ 321.474203] nouveau_display_fini+0x56/0xd0 [nouveau] [ 321.474254] nouveau_display_suspend+0x4f/0x110 [no...

...3f8471000 R14: ffffc900039f7b94 R15: ffffc900039f7bd0 > ORIG_RAX: ffffffffffffffff CS: 0010 SS: 0018 > #12 [ffffc900039f7b18] gf119_head_vblank_put at ffffffffa04422f9 [nouveau] > #13 [ffffc900039f7b88] drm_get_last_vbltimestamp at ffffffffa020ad91 [drm] > #14 [ffffc900039f7ba8] drm_update_vblank_count at ffffffffa020b3e1 [drm] > #15 [ffffc900039f7c10] drm_vblank_disable_and_save at ffffffffa020bbe9 [drm] > #16 [ffffc900039f7c40] drm_crtc_vblank_off at ffffffffa020c3c0 [drm] > #17 [ffffc900039f7cb0] nouveau_display_fini at ffffffffa048a4d6 [nouveau] > #18 [ffffc900039f7ce0] nouveau_di...

...0 [ 12.768191] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 12.768192] CR2: 000000edb16580b8 CR3: 000000020cc09000 CR4: 00000000003406f0 [ 12.768193] Call Trace: [ 12.768198] ? enqueue_task_fair+0x64/0x600 [ 12.768211] ? drm_get_last_vbltimestamp+0x47/0x70 [drm] [ 12.768223] ? drm_update_vblank_count+0x65/0x240 [drm] [ 12.768227] ? pci_pm_runtime_resume+0xa0/0xa0 [ 12.768238] ? drm_vblank_disable_and_save+0x55/0xc0 [drm] [ 12.768250] ? drm_crtc_vblank_off+0xa9/0x1e0 [drm] [ 12.768253] ? pci_pm_runtime_resume+0xa0/0xa0 [ 12.768299] ? nouveau_display_fini+0x56/0xd0 [nouveau] [ 12...

...0000000080050033 > > [ 12.768192] CR2: 000000edb16580b8 CR3: 000000020cc09000 CR4: 00000000003406f0 > > [ 12.768193] Call Trace: > > [ 12.768198] ? enqueue_task_fair+0x64/0x600 > > [ 12.768211] ? drm_get_last_vbltimestamp+0x47/0x70 [drm] > > [ 12.768223] ? drm_update_vblank_count+0x65/0x240 [drm] > > [ 12.768227] ? pci_pm_runtime_resume+0xa0/0xa0 > > [ 12.768238] ? drm_vblank_disable_and_save+0x55/0xc0 [drm] > > [ 12.768250] ? drm_crtc_vblank_off+0xa9/0x1e0 [drm] > > [ 12.768253] ? pci_pm_runtime_resume+0xa0/0xa0 > > [ 12.768299]...

...12.768192] CR2: 000000edb16580b8 CR3: 000000020cc09000 CR4: 00000000003406f0 >>>> [ 12.768193] Call Trace: >>>> [ 12.768198] ? enqueue_task_fair+0x64/0x600 >>>> [ 12.768211] ? drm_get_last_vbltimestamp+0x47/0x70 [drm] >>>> [ 12.768223] ? drm_update_vblank_count+0x65/0x240 [drm] >>>> [ 12.768227] ? pci_pm_runtime_resume+0xa0/0xa0 >>>> [ 12.768238] ? drm_vblank_disable_and_save+0x55/0xc0 [drm] >>>> [ 12.768250] ? drm_crtc_vblank_off+0xa9/0x1e0 [drm] >>>> [ 12.768253] ? pci_pm_runtime_resume+0xa0/0x...

...00 ES: 0000 CR0: 0000000080050033 > [ 321.474004] CR2: 00007fdd82e8f810 CR3: 0000000214683000 CR4: 00000000000006e0 > [ 321.474005] Call Trace: > [ 321.474068] ? nv50_head_vblank_put+0x22/0x50 [nouveau] > [ 321.474085] drm_get_last_vbltimestamp+0x41/0x70 [drm] > [ 321.474102] drm_update_vblank_count+0x61/0x230 [drm] > [ 321.474118] drm_vblank_disable_and_save+0x59/0xc0 [drm] > [ 321.474134] drm_crtc_vblank_off+0x1d5/0x210 [drm] > [ 321.474152] ? drm_modeset_drop_locks+0x4e/0x60 [drm] > [ 321.474203] nouveau_display_fini+0x56/0xd0 [nouveau] > [ 321.474254] nouveau_displ...

...et_drm_timestamp+0x40/0x40 (drivers/gpu/drm/drm_irq.c:848) ? trace_hardirqs_off+0xd/0x10 (kernel/locking/lockdep.c:2780) ? _raw_spin_unlock_irqrestore+0x4b/0x50 (kernel/locking/spinlock.c:190) ? nouveau_fence_wait_uevent_handler+0xc9/0x140 [nouveau] (drivers/gpu/drm/nouveau/nouveau_fence.c:148) drm_update_vblank_count+0x16a/0x870 (drivers/gpu/drm/drm_irq.c:150) ? store_vblank+0x2c0/0x2c0 (drivers/gpu/drm/drm_irq.c:79) drm_handle_vblank+0x14a/0x7d0 (drivers/gpu/drm/drm_irq.c:1704) ? trace_hardirqs_off+0xd/0x10 (kernel/locking/lockdep.c:2780) ? drm_crtc_wait_one_vblank+0x90/0x90 (drivers/gpu/drm/drm_irq.c:1252...

...oduleparam.h> #include <drm/drm_crtc.h> @@ -37,6 +38,8 @@ #include "drm_internal.h" #include "drm_trace.h" +#include "drm_vblank_internal.h" +#include "drm_vblank_work_internal.h" /** * DOC: vblank handling @@ -363,7 +366,7 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, store_vblank(dev, pipe, diff, t_vblank, cur_vblank); } -static u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe) +u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe) { struct drm_vblank_crtc *vblank = &dev->vblank[p...

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up