search for: drm_nouveau_gem_info

This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to specify the tiling options of a PRIME-imported buffer. The staging parameter will allow us

...rm_vma_node_offset_addr(&nvbo->bo.vma_node); rep->tile_mode = nvbo->tile_mode; - rep->tile_flags = nvbo->tile_flags; + rep->bo_flags = nvbo->bo_flags; + return 0; +} + +static int +nouveau_gem_set_info(struct drm_file *file_priv, struct drm_gem_object *gem, + struct drm_nouveau_gem_info *req) +{ + struct nouveau_bo *nvbo = nouveau_gem_object(gem); + + if (req->bo_flags & NOUVEAU_GEM_EXPLICIT_SYNC) + nvbo->bo_flags |= NOUVEAU_GEM_EXPLICIT_SYNC; + else + nvbo->bo_flags &= ~NOUVEAU_GEM_EXPLICIT_SYNC; + return 0; } @@ -231,14 +245,15 @@ nouveau_gem_ioctl_new(st...

Second version of this patchset addressing Ben's comments and fixing a few extra things. This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to

..., sizeof(req)); } } @@ -267,6 +264,7 @@ abi16_bo_init(struct nouveau_bo *bo, uint32_t alignment, union nouveau_bo_config *config) { struct nouveau_device *dev = bo->device; + struct nouveau_drm *drm = nouveau_drm(&dev->object); struct drm_nouveau_gem_new req = {}; struct drm_nouveau_gem_info *info = &req.info; int ret; @@ -309,7 +307,7 @@ abi16_bo_init(struct nouveau_bo *bo, uint32_t alignment, if (!nouveau_device(dev)->have_bo_usage) info->tile_flags &= 0x0000ff00; - ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_NEW, + ret = drmCommandWriteRead(drm->f...

...AU_GEM_DOMAIN_GART (1 << 2) @@ -141,4 +145,8 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) +#if defined(__cplusplus) +} +#endif + #endif /* __NOUVEAU_DRM_H__ */ -- 2.6.2

...507eead5863..4e7e21f41b5c 100644 > --- a/drm/nouveau/uapi/drm/nouveau_drm.h > +++ b/drm/nouveau/uapi/drm/nouveau_drm.h > @@ -140,11 +140,14 @@ struct drm_nouveau_gem_cpu_fini { > #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 > #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 > #define DRM_NOUVEAU_GEM_INFO 0x44 > +/* range 0x98..DRM_COMMAND_END (8 entries) is reserved for staging, unstable ioctls */ > +#define DRM_NOUVEAU_STAGING_IOCTL 0x58 > > #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) > #d...

...EP 0x42 >> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >> #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) >> #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >> >> +#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) >> +#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm...

...@@ struct drm_nouveau_svm_bind { >>> ? #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI?????? DRM_IOW >>> (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct >>> drm_nouveau_gem_cpu_fini) >>> ? #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >>> ? +#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) >>> +#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_NOUVEAU_VM_BIND, struct drm_nouvea...

...veau_drm.h > @@ -36,6 +36,7 @@ > #define NOUVEAU_GEM_TILE_32BPP 0x00000002 > #define NOUVEAU_GEM_TILE_ZETA 0x00000004 > #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 > +#define NOUVEAU_GEM_TILE_WCUS 0x00000010 /* write-combined, unsnooped */ > > struct drm_nouveau_gem_info { > uint32_t handle; > -- > 1.8.3.1 >

...97,6 +403,9 @@ struct drm_nouveau_svm_bind { > ?#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI? ? ? ?DRM_IOW > (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct > drm_nouveau_gem_cpu_fini) > ?#define DRM_IOCTL_NOUVEAU_GEM_INFO > ?DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct > drm_nouveau_gem_info) > > +#define DRM_IOCTL_NOUVEAU_VM_INIT > DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct > drm_nouveau_vm_init) > +#define DRM_IOCTL_NOUVEAU_VM_BIND > DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_...

...Y(nvbo, &nvdev->bo_list, head) { if (nvbo->base.handle == handle) { + pthread_mutex_unlock(&nvdev->lock); *pbo = NULL; nouveau_bo_ref(&nvbo->base, pbo); return 0; } } + pthread_mutex_unlock(&nvdev->lock); ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_INFO, &req, sizeof(req)); @@ -396,7 +418,9 @@ nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle, atomic_set(&nvbo->refcnt, 1); nvbo->base.device = dev; abi16_bo_info(&nvbo->base, &req); + pthread_mutex_lock(&nvdev->lock); DRMLISTADD(&nvbo...

...> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >>>> #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) >>>> #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >>>> +#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) >>>> +#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouvea...

From: Thierry Reding <treding at nvidia.com> This small series of patches implements support for waiting on and emitting fence FDs on kickoff. This enables explicit fencing and can be used for example to synchronize buffer accesses between the display engine and the GPU on Tegra. The first patch lays the groundwork by splitting up nouveau_fence_sync() to allow reuse. Patch 2 is where the

Hi guys, I'd like to start a new thread about explicit fence synchronization. This time with a Nouveau twist. :-) First, let me define what I understand by implicit/explicit sync: Implicit synchronization * Fences are attached to buffers * Kernel manages fences automatically based on buffer read/write access Explicit synchronization * Fences are passed around independently * Kernel takes

...t_tiling { > + uint32_t handle; > + uint32_t tile_mode; > + uint32_t tile_flags; > +}; > + > #define NOUVEAU_GEM_MAX_BUFFERS 1024 > struct drm_nouveau_gem_pushbuf_bo_presumed { > uint32_t valid; > @@ -142,6 +148,7 @@ struct drm_nouveau_gem_cpu_fini { > #define DRM_NOUVEAU_GEM_INFO 0x44 > /* range 0x98..DRM_COMMAND_END (8 entries) is reserved for staging, unstable ioctls */ > #define DRM_NOUVEAU_STAGING_IOCTL 0x58 > +#define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0) > > #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM...

...m_set_tiling { > + uint32_t handle; > + uint32_t tile_mode; > + uint32_t tile_flags; > +}; > + > #define NOUVEAU_GEM_MAX_BUFFERS 1024 > struct drm_nouveau_gem_pushbuf_bo_presumed { > uint32_t valid; > @@ -142,6 +148,7 @@ struct drm_nouveau_gem_cpu_fini { > #define DRM_NOUVEAU_GEM_INFO 0x44 > /* range 0x98..DRM_COMMAND_END (8 entries) is reserved for staging, unstable ioctls */ > #define DRM_NOUVEAU_STAGING_IOCTL 0x58 > +#define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0) > > #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_...

..._drm.h +++ b/include/uapi/drm/nouveau_drm.h @@ -36,6 +36,7 @@ #define NOUVEAU_GEM_TILE_32BPP 0x00000002 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 +#define NOUVEAU_GEM_TILE_WCUS 0x00000010 /* write-combined, unsnooped */ struct drm_nouveau_gem_info { uint32_t handle; -- 1.8.3.1

...parent->oclass == NOUVEAU_FIFO_CHANNEL_CLASS)) { + if (obj->oclass == NOUVEAU_NOTIFIER_CLASS) { + *func = abi16_ntfy; + return true; + } + + *func = abi16_engobj; + return false; + } + + *func = NULL; + return false; +} + +drm_private void abi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info) { struct nouveau_bo_priv *nvbo = nouveau_bo(bo); diff --git a/nouveau/nouveau.c b/nouveau/nouveau.c index 97fd77b..8a0be2f 100644 --- a/nouveau/nouveau.c +++ b/nouveau/nouveau.c @@ -135,6 +135,7 @@ nouveau_device_wrap(int fd, int close, struct nouveau_device **pdev) nvdev->gart_limi...

From: Ben Skeggs <bskeggs at redhat.com> This commit also modifies the install path of the main libdrm_nouveau header to be under a nouveau/ subdirectory. Signed-off-by: Ben Skeggs <bskeggs at redhat.com> --- include/drm/nouveau_drm.h | 1 + nouveau/Makefile.am | 11 +++- nouveau/libdrm_nouveau.pc.in | 2 +- nouveau/nvif/cl0080.h | 45 ++++++++++++++

...16.c */ drm_private bool abi16_object(struct nouveau_object *, int (**)(struct nouveau_object *)); drm_private void abi16_delete(struct nouveau_object *); +drm_private int abi16_sclass(struct nouveau_object *, struct nouveau_sclass **); drm_private void abi16_bo_info(struct nouveau_bo *, struct drm_nouveau_gem_info *); drm_private int abi16_bo_init(struct nouveau_bo *, uint32_t alignment, union nouveau_bo_config *); -- 2.6.3