search for: drm_iow

...TIMER_TIME 14 -#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 -#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 -struct drm_nouveau_getparam { - uint64_t param; - uint64_t value; -}; - struct drm_nouveau_setparam { uint64_t param; uint64_t value; }; -#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) #define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam) -#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, st...

This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to specify the tiling options of a PRIME-imported buffer. The staging parameter will allow us

Second version of this patchset addressing Ben's comments and fixing a few extra things. This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to

...nouveau_gem_new { @@ -149,6 +150,7 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 #define DRM_NOUVEAU_GEM_INFO 0x44 #define DRM_NOUVEAU_GEM_PUSHBUF_2 0x45 +#define DRM_NOUVEAU_GEM_SET_INFO 0x46 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) @@ -156,5 +158,6 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP...

Hi all, As some of you may know there some subtle distinction between C and C++ structs, thus one should wrap/annotate them roughly like below. ... #if defined(__cplusplus) extern "C" { #endif struct foo { int bar; ... }; ... #if defined(__cplusplus) } #endif In order to work around the lack of these users can wrap the header inclusion in the same way. For example:

...> #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 > #define DRM_NOUVEAU_GEM_INFO 0x44 > +/* range 0x98..DRM_COMMAND_END (8 entries) is reserved for staging, unstable ioctls */ > +#define DRM_NOUVEAU_STAGING_IOCTL 0x58 > > #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) > #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) > #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM...

...uot;C" { +#endif + /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints: * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit @@ -222,4 +226,8 @@ struct drm_etnaviv_gem_wait { #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) +#if defined(__cplusplus) +} +#endif + #endif /* __ETNAVIV_DRM_H__ */ -- 2.6.2

..."C" { +#endif + /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints: * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit @@ -217,4 +221,8 @@ struct drm_msm_wait_fence { #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) +#if defined(__cplusplus) +} +#endif + #endif /* __MSM_DRM_H__ */ -- 2.6.2

...splus) +extern "C" { +#endif + #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) @@ -141,4 +145,8 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) +#if defined(__cplusplus) +} +#endif + #endif /* __NOUVEAU_DRM_H__ */ -- 2.6.2

...#include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. */ @@ -114,4 +118,8 @@ struct drm_omap_gem_info { #define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini) #define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info) +#if defined(__cplusplus) +} +#endif + #endif /* __OMAP_DRM_H__ */ -- 2.6.2

From: Thierry Reding <treding at nvidia.com> This small series of patches implements support for waiting on and emitting fence FDs on kickoff. This enables explicit fencing and can be used for example to synchronize buffer accesses between the display engine and the GPU on Tegra. The first patch lays the groundwork by splitting up nouveau_fence_sync() to allow reuse. Patch 2 is where the

...0x12 >> #define DRM_NOUVEAU_GEM_NEW 0x40 >> #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 >> #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 >> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >> #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) >> #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >> >> +#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMA...

...>>> ? #define DRM_NOUVEAU_GEM_NEW??????????? 0x40 >>> ? #define DRM_NOUVEAU_GEM_PUSHBUF??????? 0x41 >>> ? #define DRM_NOUVEAU_GEM_CPU_PREP?????? 0x42 >>> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >>> ? #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI?????? DRM_IOW >>> (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct >>> drm_nouveau_gem_cpu_fini) >>> ? #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >>> ? +#define DRM_IOCTL_NOUVEAU_VM_INIT...

...? ? ? ? ? ? ? ?0x12 > ?#define DRM_NOUVEAU_GEM_NEW? ? ? ? ? ? 0x40 > ?#define DRM_NOUVEAU_GEM_PUSHBUF? ? ? ? 0x41 > ?#define DRM_NOUVEAU_GEM_CPU_PREP? ? ? ?0x42 > @@ -197,6 +403,9 @@ struct drm_nouveau_svm_bind { > ?#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI? ? ? ?DRM_IOW > (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct > drm_nouveau_gem_cpu_fini) > ?#define DRM_IOCTL_NOUVEAU_GEM_INFO > ?DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct > drm_nouveau_gem_info) > > +#define DRM_IOCTL_NOUVEAU_VM_INI...

...ine DRM_NOUVEAU_GEM_NEW 0x40 >>>> #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 >>>> #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 >>>> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >>>> #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) >>>> #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >>>> +#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_...

From: Thierry Reding <treding at nvidia.com> Hi, This series implements a new IOCTL to submit push buffers that can optionally return a sync FD or sync object to userspace. This is useful in cases where userspace wants to synchronize operations between the GPU and another driver (such as KMS for display). Among other things this allows extensions such as eglDupNativeFenceFDANDROID to be

...#define __NOUVEAU_DRM_H__ +#ifndef _UAPI_DRM_NOUVEAU_DRM_H +#define _UAPI_DRM_NOUVEAU_DRM_H #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) @@ -135,4 +135,4 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) -#endif /* __NOUVEAU_DRM_H__ */ +#endif /* _UAPI_DRM_NOUVEAU_DRM_H */ diff --git a/include/ua...

...#define __NOUVEAU_DRM_H__ +#ifndef _UAPI_DRM_NOUVEAU_DRM_H +#define _UAPI_DRM_NOUVEAU_DRM_H #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) @@ -135,4 +135,4 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) -#endif /* __NOUVEAU_DRM_H__ */ +#endif /* _UAPI_DRM_NOUVEAU_DRM_H */ diff --git a/include/ua...

...#define __NOUVEAU_DRM_H__ +#ifndef _UAPI_DRM_NOUVEAU_DRM_H +#define _UAPI_DRM_NOUVEAU_DRM_H #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) @@ -135,4 +135,4 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) -#endif /* __NOUVEAU_DRM_H__ */ +#endif /* _UAPI_DRM_NOUVEAU_DRM_H */ diff --git a/include/ua...

Hi guys, I'd like to start a new thread about explicit fence synchronization. This time with a Nouveau twist. :-) First, let me define what I understand by implicit/explicit sync: Implicit synchronization * Fences are attached to buffers * Kernel manages fences automatically based on buffer read/write access Explicit synchronization * Fences are passed around independently * Kernel takes